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[AArch64] Add v8.1a "Limited Ordering Regions" extension

Browse Source 
Reviewers: 	t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8499

Patch by: Tom Coxon


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Sukharev 2015-04-16 15:30:43 +00:00
parent 798efb5b3a
commit 39c4ba63f2
7 changed files with 101 additions and 0 deletions
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4
lib/Target/AArch64/AArch64InstrFormats.td
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@ -3288,6 +3288,10 @@ class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
: BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
bits<5> Rt;
bits<5> Rn;
let Inst{20-16} = 0b11111;
let Unpredictable{20-16} = 0b11111;
let Inst{14-10} = 0b11111;
let Unpredictable{14-10} = 0b11111;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;

14
lib/Target/AArch64/AArch64InstrInfo.td
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@ -2314,6 +2314,20 @@ def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
let Predicates = [HasV8_1a] in {
// v8.1a "Limited Order Region" extension load-acquire instructions
def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
// v8.1a "Limited Order Region" extension store-release instructions
def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
}
//===----------------------------------------------------------------------===//
// Scaled floating point to integer conversion instructions.
//===----------------------------------------------------------------------===//

8
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@ -1102,6 +1102,12 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
case AArch64::STLRW:
case AArch64::STLRB:
case AArch64::STLRH:
case AArch64::STLLRW:
case AArch64::STLLRB:
case AArch64::STLLRH:
case AArch64::LDLARW:
case AArch64::LDLARB:
case AArch64::LDLARH:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64::STLXRX:
@ -1112,6 +1118,8 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
case AArch64::LDAXRX:
case AArch64::LDXRX:
case AArch64::STLRX:
case AArch64::LDLARX:
case AArch64::STLLRX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64::STLXPW:

7
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
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@ -765,6 +765,13 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings
// v8.1a "Privileged Access Never" extension-specific system registers
{"pan", PAN, AArch64::HasV8_1aOps},
// v8.1a "Limited Ordering Regions" extension-specific system registers
{"lorsa_el1", LORSA_EL1, AArch64::HasV8_1aOps},
{"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
{"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
{"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
{"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
};
uint32_t

7
lib/Target/AArch64/Utils/AArch64BaseInfo.h
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@ -1141,6 +1141,13 @@ namespace AArch64SysReg {
// v8.1a "Privileged Access Never" extension-specific system registers
PAN = 0xc213, // 11 000 0100 0010 011
// v8.1a "Limited Ordering Regions" extension-specific system registers
LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
LORN_EL1 = 0xc522, // 11 000 1010 0100 010
LORC_EL1 = 0xc523, // 11 000 1010 0100 011
LORID_EL1 = 0xc527, // 11 000 1010 0100 111
// Cyclone specific system registers
CPM_IOACC_CTL_EL3 = 0xff90,
};

33
test/MC/AArch64/armv8.1a-lor.s Normal file
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@ -0,0 +1,33 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
//------------------------------------------------------------------------------
// Load acquire / store release
//------------------------------------------------------------------------------
ldlarb w0,[x1]
ldlarh w0,[x1]
ldlar w0,[x1]
ldlar x0,[x1]
// CHECK: ldlarb w0, [x1] // encoding: [0x20,0x7c,0xdf,0x08]
// CHECK: ldlarh w0, [x1] // encoding: [0x20,0x7c,0xdf,0x48]
// CHECK: ldlar w0, [x1] // encoding: [0x20,0x7c,0xdf,0x88]
// CHECK: ldlar x0, [x1] // encoding: [0x20,0x7c,0xdf,0xc8]
stllrb w0,[x1]
stllrh w0,[x1]
stllr w0,[x1]
stllr x0,[x1]
// CHECK: stllrb w0, [x1] // encoding: [0x20,0x7c,0x9f,0x08]
// CHECK: stllrh w0, [x1] // encoding: [0x20,0x7c,0x9f,0x48]
// CHECK: stllr w0, [x1] // encoding: [0x20,0x7c,0x9f,0x88]
// CHECK: stllr x0, [x1] // encoding: [0x20,0x7c,0x9f,0xc8]
msr LORSA_EL1, x0
msr LOREA_EL1, x0
msr LORN_EL1, x0
msr LORC_EL1, x0
mrs x0, LORID_EL1
// CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
// CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
// CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5]
// CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5]
// CHECK: mrs x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]

28
test/MC/Disassembler/AArch64/armv8.1a-lor.txt Normal file
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@ -0,0 +1,28 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
0x20,0x7c,0xdf,0x08
0x20,0x7c,0xdf,0x48
0x20,0x7c,0xdf,0x88
0x20,0x7c,0xdf,0xc8
0x20,0x7c,0x9f,0x08
0x20,0x7c,0x9f,0x48
0x20,0x7c,0x9f,0x88
0x20,0x7c,0x9f,0xc8
# CHECK: ldlarb w0, [x1]
# CHECK: ldlarh w0, [x1]
# CHECK: ldlar w0, [x1]
# CHECK: ldlar x0, [x1]
# CHECK: stllrb w0, [x1]
# CHECK: stllrh w0, [x1]
# CHECK: stllr w0, [x1]
# CHECK: stllr x0, [x1]
0x00,0xa4,0x18,0xd5
0x20,0xa4,0x18,0xd5
0x40,0xa4,0x18,0xd5
0x60,0xa4,0x18,0xd5
0xe0,0xa4,0x38,0xd5
# CHECK: msr LORSA_EL1, x0
# CHECK: msr LOREA_EL1, x0
# CHECK: msr LORN_EL1, x0
# CHECK: msr LORC_EL1, x0
# CHECK: mrs x0, LORID_EL1