6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-13 23:25:06 +00:00
Code Issues Projects Releases Wiki Activity

Tidy up. Naming conventions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155960 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2012-05-01 23:21:41 +00:00
parent dca40aa911
commit 39cc513870
1 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
lib/CodeGen/PeepholeOptimizer.cpp
View File

@@ -95,14 +95,14 @@ namespace {
} }
private: private:
bool OptimizeBitcastInstr(MachineInstr *MI, MachineBasicBlock *MBB); bool optimizeBitcastInstr(MachineInstr *MI, MachineBasicBlock *MBB);
bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB); bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
bool OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSet<MachineInstr*, 8> &LocalMIs); SmallPtrSet<MachineInstr*, 8> &LocalMIs);
bool isMoveImmediate(MachineInstr *MI, bool isMoveImmediate(MachineInstr *MI,
SmallSet<unsigned, 4> &ImmDefRegs, SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs); DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
bool FoldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
SmallSet<unsigned, 4> &ImmDefRegs, SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs); DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
}; };
@@ -116,7 +116,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts", INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
"Peephole Optimizations", false, false) "Peephole Optimizations", false, false)
/// OptimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads /// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
/// a single register and writes a single register and it does not modify the /// a single register and writes a single register and it does not modify the
/// source, and if the source value is preserved as a sub-register of the /// source, and if the source value is preserved as a sub-register of the
/// result, then replace all reachable uses of the source with the subreg of the /// result, then replace all reachable uses of the source with the subreg of the
@@ -126,7 +126,7 @@ INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
/// the code. Since this code does not currently share EXTRACTs, just ignore all /// the code. Since this code does not currently share EXTRACTs, just ignore all
/// debug uses. /// debug uses.
bool PeepholeOptimizer:: bool PeepholeOptimizer::
OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSet<MachineInstr*, 8> &LocalMIs) { SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
unsigned SrcReg, DstReg, SubIdx; unsigned SrcReg, DstReg, SubIdx;
if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
@@ -255,7 +255,7 @@ OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
return Changed; return Changed;
} }
/// OptimizeBitcastInstr - If the instruction is a bitcast instruction A that /// optimizeBitcastInstr - If the instruction is a bitcast instruction A that
/// cannot be optimized away during isel (e.g. ARM::VMOVSR, which bitcast /// cannot be optimized away during isel (e.g. ARM::VMOVSR, which bitcast
/// a value cross register classes), and the source is defined by another /// a value cross register classes), and the source is defined by another
/// bitcast instruction B. And if the register class of source of B matches /// bitcast instruction B. And if the register class of source of B matches
@@ -265,7 +265,7 @@ OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
/// %vreg3<def> = VMOVRS %vreg0 /// %vreg3<def> = VMOVRS %vreg0
/// Replace all uses of vreg3 with vreg1. /// Replace all uses of vreg3 with vreg1.
bool PeepholeOptimizer::OptimizeBitcastInstr(MachineInstr *MI, bool PeepholeOptimizer::optimizeBitcastInstr(MachineInstr *MI,
MachineBasicBlock *MBB) { MachineBasicBlock *MBB) {
unsigned NumDefs = MI->getDesc().getNumDefs(); unsigned NumDefs = MI->getDesc().getNumDefs();
unsigned NumSrcs = MI->getDesc().getNumOperands() - NumDefs; unsigned NumSrcs = MI->getDesc().getNumOperands() - NumDefs;
@@ -327,11 +327,11 @@ bool PeepholeOptimizer::OptimizeBitcastInstr(MachineInstr *MI,
return true; return true;
} }
/// OptimizeCmpInstr - If the instruction is a compare and the previous /// optimizeCmpInstr - If the instruction is a compare and the previous
/// instruction it's comparing against all ready sets (or could be modified to /// instruction it's comparing against all ready sets (or could be modified to
/// set) the same flag as the compare, then we can remove the comparison and use /// set) the same flag as the compare, then we can remove the comparison and use
/// the flag from the previous instruction. /// the flag from the previous instruction.
bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI, bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
MachineBasicBlock *MBB) { MachineBasicBlock *MBB) {
// If this instruction is a comparison against zero and isn't comparing a // If this instruction is a comparison against zero and isn't comparing a
// physical register, we can try to optimize it. // physical register, we can try to optimize it.
@@ -368,10 +368,10 @@ bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
return false; return false;
} }
/// FoldImmediate - Try folding register operands that are defined by move /// foldImmediate - Try folding register operands that are defined by move
/// immediate instructions, i.e. a trivial constant folding optimization, if /// immediate instructions, i.e. a trivial constant folding optimization, if
/// and only if the def and use are in the same BB. /// and only if the def and use are in the same BB.
bool PeepholeOptimizer::FoldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
SmallSet<unsigned, 4> &ImmDefRegs, SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) { DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
@@ -430,7 +430,7 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
} }
if (MI->isBitcast()) { if (MI->isBitcast()) {
if (OptimizeBitcastInstr(MI, MBB)) { if (optimizeBitcastInstr(MI, MBB)) {
// MI is deleted. // MI is deleted.
LocalMIs.erase(MI); LocalMIs.erase(MI);
Changed = true; Changed = true;
@@ -438,7 +438,7 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
continue; continue;
} }
} else if (MI->isCompare()) { } else if (MI->isCompare()) {
if (OptimizeCmpInstr(MI, MBB)) { if (optimizeCmpInstr(MI, MBB)) {
// MI is deleted. // MI is deleted.
LocalMIs.erase(MI); LocalMIs.erase(MI);
Changed = true; Changed = true;
@@ -450,9 +450,9 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) { if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
SeenMoveImm = true; SeenMoveImm = true;
} else { } else {
Changed |= OptimizeExtInstr(MI, MBB, LocalMIs); Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
if (SeenMoveImm) if (SeenMoveImm)
Changed |= FoldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs); Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
} }
First = false; First = false;