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Add assertion to detect invalid registers in the PowerPC MC instruction lowering.

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We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232525 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Samuel Antao 2015-03-17 19:31:19 +00:00
parent 51b4d85c62
commit 3a660c933a
1 changed files with 3 additions and 0 deletions
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lib/Target/PowerPC/PPCMCInstLower.cpp
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@ -184,6 +184,9 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
assert(!MO.getSubReg() && "Subregs should be eliminated!");
assert(MO.getReg() > PPC::NoRegister &&
MO.getReg() < PPC::NUM_TARGET_REGS &&
"Invalid register for this target!");
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate: