6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 21:32:39 +00:00
Code Issues Projects Releases Wiki Activity

[X86] Specify all TSFlags bit-offsets symbolically

Browse Source 
No functional change.

The offsets for the other bitfields are specified symbolically.  I need to
increase the size for one of the earlier fields which is easier after this
cleanup.

Why these bits are relative to VEXShift is a bit strange but that is for
another cleanup.

I made sure that the values for the enums are unchanged after this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213011 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-07-14 23:18:39 +00:00
parent 38d8be1ad8
commit 3afd71fc7d
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -534,14 +534,17 @@ namespace X86II {
/// storing a classifier in the imm8 field. To simplify our implementation,
/// we handle this by storeing the classifier in the opcode field and using
/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
Has3DNow0F0FOpcode = 1U << 15,
Has3DNow0F0FOpcodeShift = EVEX_CD8VShift + 3,
Has3DNow0F0FOpcode = 1U << (Has3DNow0F0FOpcodeShift - VEXShift),
/// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
/// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
MemOp4 = 1U << 16,
MemOp4Shift = Has3DNow0F0FOpcodeShift + 1,
MemOp4 = 1U << (MemOp4Shift - VEXShift),
/// Explicitly specified rounding control
EVEX_RC = 1U << 17
EVEX_RCShift = MemOp4Shift + 1,
EVEX_RC = 1U << (EVEX_RCShift - VEXShift)
};
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the