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Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149097 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -553,10 +553,12 @@ bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
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if (UIdx != -1) {
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ValLREndInst->getOperand(UIdx).setIsKill(false);
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}
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// If the copy instruction was killing the destination register before the
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// merge, find the last use and trim the live range. That will also add the
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// isKill marker.
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// Rewrite the copy. If the copy instruction was killing the destination
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// register before the merge, find the last use and trim the live range. That
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// will also add the isKill marker.
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CopyMI->substituteRegister(IntA.reg, IntB.reg, CP.getSubIdx(),
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*TRI);
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if (ALR->end == CopyIdx)
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LIS->shrinkToUses(&IntA);
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21
test/CodeGen/ARM/2012-01-26-CoalescerBug.ll
Normal file
21
test/CodeGen/ARM/2012-01-26-CoalescerBug.ll
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@ -0,0 +1,21 @@
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; RUN: llc < %s -verify-coalescing
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; PR11861
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-eabi"
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define arm_aapcs_vfpcc void @foo() nounwind uwtable align 2 {
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br label %1
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; <label>:1 ; preds = %1, %0
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%2 = phi <4 x float> [ undef, %0 ], [ %11, %1 ]
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%3 = bitcast <4 x float> %2 to <2 x i64>
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%4 = shufflevector <2 x i64> %3, <2 x i64> undef, <1 x i32> zeroinitializer
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%5 = xor <2 x i32> zeroinitializer, <i32 -1, i32 -1>
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%6 = bitcast <2 x i32> zeroinitializer to <2 x float>
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%7 = shufflevector <2 x float> zeroinitializer, <2 x float> %6, <2 x i32> <i32 0, i32 2>
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%8 = shufflevector <2 x i64> %3, <2 x i64> undef, <1 x i32> <i32 1>
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%9 = bitcast <2 x float> %7 to <1 x i64>
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%10 = shufflevector <1 x i64> %9, <1 x i64> %8, <2 x i32> <i32 0, i32 1>
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%11 = bitcast <2 x i64> %10 to <4 x float>
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br label %1
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}
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