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Update PPCRegisterInfo's use of virtual registers to be SSA

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PPC's use of PEI's virtual-register-based scavenging functionality had
redefined the virtual registers (it was non-SSA). Now that PEI supports
dealing with instructions with multiple virtual registers, this can be
cleanup up to use multiple virtual registers and keep SSA form.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2013-03-26 18:57:20 +00:00
parent 8846129f6e
commit 3b196f20fb
1 changed files with 5 additions and 3 deletions
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8
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@@ -578,13 +578,15 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC); const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
SReg = MF.getRegInfo().createVirtualRegister(RC);
// Insert a set of rA with the full offset value before the ld, st, or add // Insert a set of rA with the full offset value before the ld, st, or add
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
.addImm(Offset >> 16); .addImm(Offset >> 16);
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
.addReg(SReg, RegState::Kill) .addReg(SRegHi, RegState::Kill)
.addImm(Offset); .addImm(Offset);
// Convert into indexed form of the instruction: // Convert into indexed form of the instruction: