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simplify some code by using shorter accessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45622 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -135,11 +135,13 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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// Loads from constant pools are trivially rematerializable.
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return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
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MI->getOperand(1).getReg() == 0 &&
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MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(3).getReg() == 0;
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if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
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MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
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MI->getOperand(1).getReg() == 0 &&
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MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(3).getReg() == 0)
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return true;
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return false;
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}
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// All other instructions marked M_REMATERIALIZABLE are always trivially
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// rematerializable.
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@ -161,10 +163,8 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
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// Loads from global addresses which aren't redefined in the function are
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// side effect free.
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if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() &&
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MI->getOperand(4).isGlobalAddress() &&
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MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
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MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(3).getReg() == 0)
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return true;
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}
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@ -181,14 +181,14 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
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case X86::MOVAPDrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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// Loads from constant pools have no side effects
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return MI->getOperand(1).isRegister() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() &&
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MI->getOperand(4).isConstantPoolIndex() &&
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MI->getOperand(1).getReg() == 0 &&
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MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(3).getReg() == 0;
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// Loads from constant pools are trivially rematerializable.
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if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
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MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
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MI->getOperand(1).getReg() == 0 &&
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MI->getOperand(2).getImm() == 1 &&
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MI->getOperand(3).getReg() == 0)
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return true;
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return false;
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}
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// All other instances of these instructions are presumed to have side
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