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simplify some code by using shorter accessors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-05 05:28:30 +00:00
parent a83b34bbeb
commit 3b5a221f81
1 changed files with 17 additions and 17 deletions
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26
lib/Target/X86/X86InstrInfo.cpp
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@ -135,11 +135,13 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
case X86::MMX_MOVD64rm: case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm: case X86::MMX_MOVQ64rm:
// Loads from constant pools are trivially rematerializable. // Loads from constant pools are trivially rematerializable.
return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
MI->getOperand(1).getReg() == 0 && MI->getOperand(1).getReg() == 0 &&
MI->getOperand(2).getImm() == 1 && MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0; MI->getOperand(3).getReg() == 0)
return true;
return false;
} }
// All other instructions marked M_REMATERIALIZABLE are always trivially // All other instructions marked M_REMATERIALIZABLE are always trivially
// rematerializable. // rematerializable.
@ -161,10 +163,8 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
// Loads from global addresses which aren't redefined in the function are // Loads from global addresses which aren't redefined in the function are
// side effect free. // side effect free.
if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) && if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
MI->getOperand(2).isImmediate() && MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isGlobal() && MI->getOperand(2).getImm() == 1 &&
MI->getOperand(4).isGlobalAddress() &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0) MI->getOperand(3).getReg() == 0)
return true; return true;
} }
@ -181,14 +181,14 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
case X86::MOVAPDrm: case X86::MOVAPDrm:
case X86::MMX_MOVD64rm: case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm: case X86::MMX_MOVQ64rm:
// Loads from constant pools have no side effects // Loads from constant pools are trivially rematerializable.
return MI->getOperand(1).isRegister() && if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
MI->getOperand(2).isImmediate() && MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 && MI->getOperand(1).getReg() == 0 &&
MI->getOperand(2).getImm() == 1 && MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0; MI->getOperand(3).getReg() == 0)
return true;
return false;
} }
// All other instances of these instructions are presumed to have side // All other instances of these instructions are presumed to have side