6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00
Code Issues Projects Releases Wiki Activity

Added ARM::CPSR to represent ARM CPSR status register.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37894 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-05 07:11:03 +00:00
parent 7e36966de4
commit 3b5b8368f3
1 changed files with 59 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

108
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -144,14 +144,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addFrameIndex(FI).addImm(0);
else
BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
.addReg(0);
} else if (RC == ARM::DPRRegisterClass) {
BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
}
}
@ -167,14 +168,15 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addFrameIndex(FI).addImm(0);
else
BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
.addReg(0);
} else if (RC == ARM::DPRRegisterClass) {
BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL);
.addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
}
}
@ -189,13 +191,13 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
else
BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
.addImm((int64_t)ARMCC::AL);
.addImm((int64_t)ARMCC::AL).addReg(0);
} else if (RC == ARM::SPRRegisterClass)
BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
.addImm((int64_t)ARMCC::AL);
.addImm((int64_t)ARMCC::AL).addReg(0);
else if (RC == ARM::DPRRegisterClass)
BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg)
.addImm((int64_t)ARMCC::AL);
.addImm((int64_t)ARMCC::AL).addReg(0);
else
abort();
}
@ -204,7 +206,8 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
/// specified immediate.
static void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, ARMCC::CondCodes Pred, int Val,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred, unsigned PredReg,
const TargetInstrInfo &TII, bool isThumb) {
MachineFunction &MF = *MBB.getParent();
MachineConstantPool *ConstantPool = MF.getConstantPool();
@ -214,7 +217,7 @@ static void emitLoadConstPool(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
else
BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
.addReg(0).addImm(0).addImm((unsigned)Pred);
.addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
}
void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
@ -223,8 +226,9 @@ void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
const MachineInstr *Orig) const {
if (Orig->getOpcode() == ARM::MOVi2pieces) {
emitLoadConstPool(MBB, I, DestReg,
(ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
Orig->getOperand(1).getImmedValue(),
(ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
Orig->getOperand(3).getReg(),
TII, false);
return;
}
@ -255,14 +259,15 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
default: break;
case ARM::MOVr: {
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
.addReg(0).addImm(0).addImm(Pred);
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
.addImm(0).addImm(Pred);
.addImm(0).addImm(Pred).addReg(PredReg);
}
break;
}
@ -286,27 +291,29 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
}
case ARM::FCPYS: {
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
.addImm(0).addImm(Pred);
.addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
.addImm(0).addImm(Pred);
.addImm(0).addImm(Pred).addReg(PredReg);
}
break;
}
case ARM::FCPYD: {
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
.addImm(0).addImm(Pred);
.addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
.addImm(0).addImm(Pred);
.addImm(0).addImm(Pred).addReg(PredReg);
}
break;
}
@ -426,9 +433,9 @@ bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
static
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, unsigned BaseReg,
ARMCC::CondCodes Pred,
int NumBytes, const TargetInstrInfo &TII) {
unsigned DestReg, unsigned BaseReg, int NumBytes,
ARMCC::CondCodes Pred, unsigned PredReg,
const TargetInstrInfo &TII) {
bool isSub = NumBytes < 0;
if (isSub) NumBytes = -NumBytes;
@ -447,7 +454,7 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
// Build the new ADD / SUB.
BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
.addReg(BaseReg, false, false, true).addImm(SOImmVal)
.addImm((unsigned)Pred);
.addImm((unsigned)Pred).addReg(PredReg, false);
BaseReg = DestReg;
}
}
@ -512,7 +519,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, false, false, true);
} else
emitLoadConstPool(MBB, MBBI, LdReg, ARMCC::AL, NumBytes, TII, true);
emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@ -632,12 +639,13 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
static
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
ARMCC::CondCodes Pred, int NumBytes, bool isThumb,
const TargetInstrInfo &TII) {
int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
bool isThumb, const TargetInstrInfo &TII) {
if (isThumb)
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
else
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, Pred, NumBytes, TII);
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
Pred, PredReg, TII);
}
void ARMRegisterInfo::
@ -662,11 +670,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
bool isThumb = AFI->isThumbFunction();
ARMCC::CondCodes Pred = isThumb
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
emitSPUpdate(MBB, I, Pred, -Amount, isThumb, TII);
emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
} else {
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
emitSPUpdate(MBB, I, Pred, Amount, isThumb, TII);
emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
}
}
}
@ -944,7 +953,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
else {
emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true);
emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
UseRR = true;
}
} else
@ -979,7 +988,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
else {
emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true);
emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
UseRR = true;
}
} else
@ -1012,8 +1021,9 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred,
isSub ? -Offset : Offset, TII);
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, Pred, PredReg, TII);
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
}
}
@ -1315,11 +1325,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
int FramePtrSpillFI = 0;
if (VARegSaveSize)
emitSPUpdate(MBB, MBBI, ARMCC::AL, -VARegSaveSize, isThumb, TII);
emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
if (!AFI->hasStackFrame()) {
if (NumBytes != 0)
emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII);
emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
return;
}
@ -1359,7 +1369,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (!isThumb) {
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS1Size, isThumb, TII);
emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
} else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
++MBBI;
@ -1370,16 +1380,16 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
.addFrameIndex(FramePtrSpillFI).addImm(0);
if (!isThumb) MIB.addImm(ARMCC::AL);
if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0);
}
if (!isThumb) {
// Build the new SUBri to adjust SP for integer callee-save spill area 2.
emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS2Size, false, TII);
emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
// Build the new SUBri to adjust SP for FP callee-save spill area.
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
emitSPUpdate(MBB, MBBI, ARMCC::AL, -DPRCSSize, false, TII);
emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
}
// Determine starting offsets of spill areas.
@ -1396,7 +1406,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Insert it after all the callee-save spills.
if (!isThumb)
movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII);
emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
}
if(STI.isTargetELF() && hasFP(MF)) {
@ -1439,7 +1449,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
int NumBytes = (int)MFI->getStackSize();
if (!AFI->hasStackFrame()) {
if (NumBytes != 0)
emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII);
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
} else {
// Unwind MBBI to point to first LDR / FLDD.
const unsigned *CSRegs = getCalleeSavedRegs();
@ -1469,9 +1479,9 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
&MBB.front() != MBBI &&
prior(MBBI)->getOpcode() == ARM::tPOP) {
MachineBasicBlock::iterator PMBBI = prior(MBBI);
emitSPUpdate(MBB, PMBBI, ARMCC::AL, NumBytes, isThumb, TII);
emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
} else
emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII);
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
}
} else {
// Darwin ABI requires FP to point to the stack slot that contains the
@ -1486,27 +1496,27 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
hasFP(MF))
if (NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
.addImm(NumBytes).addImm((unsigned)ARMCC::AL);
.addImm(NumBytes).addImm((unsigned)ARMCC::AL).addReg(0);
else
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL);
.addImm((unsigned)ARMCC::AL).addReg(0);
} else if (NumBytes) {
emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, false, TII);
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
}
// Move SP to start of integer callee save spill area 2.
movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getDPRCalleeSavedAreaSize(),
emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
false, TII);
// Move SP to start of integer callee save spill area 1.
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea2Size(),
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
false, TII);
// Move SP to SP upon entry to the function.
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea1Size(),
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
false, TII);
}
}
@ -1517,7 +1527,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
// FIXME: Verify this is still ok when R3 is no longer being reserved.
BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
emitSPUpdate(MBB, MBBI, ARMCC::AL, VARegSaveSize, isThumb, TII);
emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
if (isThumb) {
BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);