6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Add an entry.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135024 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-13 01:33:00 +00:00
parent 61905f0139
commit 3b737081e4
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/README.txt
View File

@ -681,3 +681,21 @@ is compiled and optimized to:
str r1, [r0]
//===---------------------------------------------------------------------===//
Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1
ARM codegen used to look like this:
mov r1, r0
cmp r1, #1
mov r0, #0
moveq r0, #1
The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
cmp r0, #1
movne r0, #0
Currently this is a ARM specific dag combine. We probably should make it into a
target-neutral one.