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[mips][FastISel] Apply only zero-extension to constants prior to their materialization.
Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -290,12 +290,7 @@ unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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const ConstantInt *CI = cast<ConstantInt>(C);
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int64_t Imm;
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if ((VT != MVT::i1) && CI->isNegative())
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Imm = CI->getSExtValue();
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else
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Imm = CI->getZExtValue();
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return materialize32BitInt(Imm, RC);
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return materialize32BitInt(CI->getZExtValue(), RC);
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}
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unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
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