mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
Fix comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112202 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
767b5b6227
commit
3b7bbfd36c
@ -50,7 +50,7 @@ namespace llvm {
|
||||
CALL, // PIC16 Call instruction
|
||||
CALLW, // PIC16 CALLW instruction
|
||||
SUBCC, // Compare for equality or inequality.
|
||||
SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond.
|
||||
SELECT_ICC, // Pseudo to be caught in scheduler and expanded to brcond.
|
||||
BRCOND, // Conditional branch.
|
||||
RET, // Return.
|
||||
Dummy
|
||||
|
@ -153,7 +153,7 @@ def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
|
||||
def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
|
||||
}
|
||||
|
||||
// FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
|
||||
// FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
|
||||
// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
|
||||
// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
|
||||
// f80 instructions cannot use SSE and use neither of these.
|
||||
|
@ -211,7 +211,7 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
|
||||
class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
|
||||
: I<o, F, outs, ins, asm, []> {}
|
||||
|
||||
// FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
|
||||
// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
|
||||
class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
|
||||
: X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
|
||||
let FPForm = fp;
|
||||
|
Loading…
Reference in New Issue
Block a user