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Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-07 00:42:42 +00:00
parent 1bb9adae4c
commit 3bbdcea49a
4 changed files with 32 additions and 17 deletions
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18
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -193,7 +193,7 @@ private:
SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag); SDValue InFlag);
SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, ARMCC::CondCodes CCVal, SDValue CCR,
SDValue InFlag); SDValue InFlag);
@ -1521,18 +1521,20 @@ SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
} }
SDNode *ARMDAGToDAGISel:: SDNode *ARMDAGToDAGISel::
SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
if (!T) if (!T)
return 0; return 0;
if (Pred_so_imm(TrueVal.getNode())) { unsigned TrueImm = T->getZExtValue();
SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); bool isSoImm = Pred_so_imm(TrueVal.getNode());
if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) {
SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
return CurDAG->SelectNodeTo(N, return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::MOVCCi : ARM::MOVCCi16),
ARM::MOVCCi, MVT::i32, Ops, 5); MVT::i32, Ops, 5);
} }
return 0; return 0;
} }
@ -1589,10 +1591,10 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
if (Res) if (Res)
return Res; return Res;
} else { } else {
SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal, SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
CCVal, CCR, InFlag); CCVal, CCR, InFlag);
if (!Res) if (!Res)
Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal, Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
ARMCC::getOppositeCondition(CCVal), CCR, InFlag); ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
if (Res) if (Res)
return Res; return Res;

13
lib/Target/ARM/ARMInstrInfo.td
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@ -2416,6 +2416,9 @@ def BCCZi64 : PseudoInst<(outs),
// Conditional moves // Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
// FIXME: These should all be pseudo-instructions that get expanded to
// the normal MOV instructions. That would fix the dependency on
// special casing them in tblgen.
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
IIC_iCMOVr, "mov", "\t$dst, $true", IIC_iCMOVr, "mov", "\t$dst, $true",
@ -2433,6 +2436,16 @@ def MOVCCs : AI1<0b1101, (outs GPR:$dst),
let Inst{25} = 0; let Inst{25} = 0;
} }
def MOVCCi16 : AI1<0b1000, (outs GPR:$dst), (ins GPR:$false, i32imm:$src),
DPFrm, IIC_iMOVi,
"movw", "\t$dst, $src",
[]>,
RegConstraint<"$false = $dst">, Requires<[IsARM, HasV6T2]>,
UnaryDP {
let Inst{20} = 0;
let Inst{25} = 1;
}
def MOVCCi : AI1<0b1101, (outs GPR:$dst), def MOVCCi : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
"mov", "\t$dst, $true", "mov", "\t$dst, $true",

4
test/CodeGen/ARM/select-imm.ll
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@ -25,8 +25,8 @@ entry:
; ARM: movle r0, #123 ; ARM: movle r0, #123
; T2: t2: ; T2: t2:
; T2: movw r0, #357 ; T2: mov r0, #123
; T2: movle r0, #123 ; T2: movwgt r0, #357
%0 = icmp sgt i32 %c, 1 %0 = icmp sgt i32 %c, 1
%1 = select i1 %0, i32 357, i32 123 %1 = select i1 %0, i32 357, i32 123

14
utils/TableGen/ARMDecoderEmitter.cpp
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@ -1610,13 +1610,13 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
// better off using the generic RSCri and RSCrs instructions. // better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false; if (Name == "RSCSri" || Name == "RSCSrs") return false;
// MOVCCr, MOVCCs, MOVCCi, FCYPScc, FCYPDcc, FNEGScc, and FNEGDcc are used // MOVCCr, MOVCCs, MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and
// in the compiler to implement conditional moves. We can ignore them in // FNEGDcc are used in the compiler to implement conditional moves.
// favor of their more generic versions of instructions. // We can ignore them in favor of their more generic versions of
// See also SDNode *ARMDAGToDAGISel::Select(SDValue Op). // instructions. See also SDNode *ARMDAGToDAGISel::Select(SDValue Op).
if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" || if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" ||
Name == "FCPYScc" || Name == "FCPYDcc" || Name == "MOVCCi16" || Name == "FCPYScc" || Name == "FCPYDcc" ||
Name == "FNEGScc" || Name == "FNEGDcc") Name == "FNEGScc" || Name == "FNEGDcc")
return false; return false;
// Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc. // Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc.