mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-03 00:33:09 +00:00
*** Implement frame pointer elimination on X86!
* Include contents of X86RegisterClasses.cpp into here * Adjustments to register api to work with new frame manager * Eliminate moveImm2Reg, getFramePointer, and getStackPointer * Cleanup and simplify prolog/epilog code generation * Prolog/epilog are MUCH more efficient now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5186 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
e0a3fcb304
commit
3c1c03d7a7
@ -1,6 +1,7 @@
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//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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//
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// This file contains the X86 implementation of the MRegisterInfo class.
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// This file contains the X86 implementation of the MRegisterInfo class. This
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// file is responsible for the frame pointer elimination optimization on X86.
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//
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//===----------------------------------------------------------------------===//
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@ -11,9 +12,17 @@
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/FunctionFrameInfo.h"
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#include "Support/CommandLine.h"
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namespace {
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cl::opt<bool>
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NoFPElim("no-fp-elim",
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cl::desc("Disable frame pointer elimination optimization"));
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}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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switch (RC->getDataSize()) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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@ -22,99 +31,321 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
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}
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}
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void X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned SrcReg, unsigned DestReg,
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unsigned ImmOffset,
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const TargetRegisterClass *RC) const {
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void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
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MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 5),
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DestReg, ImmOffset).addReg(SrcReg);
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MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
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FrameIdx).addReg(SrcReg);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::loadRegOffset2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned SrcReg,
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unsigned ImmOffset,
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const TargetRegisterClass *RC) const {
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void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const{
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static const unsigned Opcode[] =
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{ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
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MachineInstr *MI = addRegOffset(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
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SrcReg, ImmOffset);
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MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
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FrameIdx);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::moveReg2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
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MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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void X86RegisterInfo::moveImm2Reg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned Imm,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOVir8, X86::MOVir16, X86::MOVir32, 0 };
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MachineInstr *MI = BuildMI(Opcode[getIdx(RC)], 1, DestReg).addReg(Imm);
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assert(MI->getOpcode() != 0 && "Cannot move FP imm to reg yet!");
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MBBI = MBB.insert(MBBI, MI)+1;
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}
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unsigned X86RegisterInfo::getFramePointer() const {
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return X86::EBP;
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}
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unsigned X86RegisterInfo::getStackPointer() const {
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return X86::ESP;
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}
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const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = { X86::ESI, X86::EDI, X86::EBX, 0 };
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static const unsigned CalleeSaveRegs[] = {
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X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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return CalleeSaveRegs;
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}
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const unsigned* X86RegisterInfo::getCallerSaveRegs() const {
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static const unsigned CallerSaveRegs[] = { X86::EAX, X86::ECX, X86::EDX, 0 };
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return CallerSaveRegs;
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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void X86RegisterInfo::emitPrologue(MachineFunction &MF,
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unsigned NumBytes) const {
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// hasSPAdjust - Return true if this function has ESP adjustment instructions in
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// the prolog and epilog which allocate local stack space. This is neccesary
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// because we elide these instructions if there are no function calls in the
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// current function (ie, this is a leaf function). In this case, we can refer
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// beyond the stack pointer because we know that nothing will trample on that
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// part of the stack.
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//
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static bool hasSPAdjust(MachineFunction &MF) {
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assert(!hasFP(MF) && "Can only eliminate SP adjustment if no frame-pointer!");
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return MF.getFrameInfo()->hasCalls();
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}
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void X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) const {
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MachineInstr *New = 0, *Old = *I;;
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if (hasFP(MF)) {
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// If we have a frame pointer, turn the adjcallstackup instruction into a
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// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
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// <amt>'
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
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New=BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
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} else {
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assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
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New=BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
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}
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}
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}
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if (New)
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*I = New; // Replace the pseudo instruction with a new instruction...
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else
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I = MBB.erase(I);// Just delete the pseudo instruction...
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delete Old;
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}
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void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator &II) const {
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unsigned i = 3;
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MachineInstr &MI = **II;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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// This must be part of a four operand memory reference. Replace the
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// FrameIndex with the offset and the base register with EBP.
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MI.SetMachineOperandReg(i-3, hasFP(MF) ? X86::EBP : X86::ESP);
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// Now replace the frame index itself with the offset from EBP.
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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if (!hasFP(MF) && hasSPAdjust(MF)) {
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const FunctionFrameInfo *FFI = MF.getFrameInfo();
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Offset += FFI->getStackSize() + FFI->getMaxCallFrameSize();
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}
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MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
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}
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void X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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const {
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if (hasFP(MF)) {
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// Create a frame entry for the EBP register that must be saved.
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int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
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assert(FrameIdx == MF.getFrameInfo()->getObjectIndexEnd()-1 &&
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"Slot for EBP register must be last in order to be found!");
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}
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}
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void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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const FunctionFrameInfo *FFI = MF.getFrameInfo();
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MachineInstr *MI;
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// Round stack allocation up to a nice alignment to keep the stack aligned
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NumBytes = (NumBytes + 3) & ~3;
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = FFI->getStackSize();
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if (hasFP(MF)) {
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// Get the offset of the stack slot for the EBP register... which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1);
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// PUSH ebp
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MachineInstr *MI = BuildMI(X86::PUSHr32, 1).addReg(X86::EBP);
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MBBI = MBB.insert(MBBI, MI)+1;
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MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
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X86::ESP, EBPOffset).addReg(X86::EBP);
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MBBI = MBB.insert(MBBI, MI)+1;
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MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
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MBBI = MBB.insert(MBBI, MI)+1;
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} else {
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// If we don't have a frame pointer, and the function contains no call sites
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// (it's a leaf function), we don't have to emit ANY stack adjustment
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// instructions at all, we can just refer to the area beyond the stack
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// pointer. This can be important for small functions.
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//
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if (!hasSPAdjust(MF)) return;
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// MOV ebp, esp
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MI = BuildMI(X86::MOVrr32, 1, X86::EBP).addReg(X86::ESP);
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MBBI = MBB.insert(MBBI, MI)+1;
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// When we have no frame pointer, we reserve argument space for call sites
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// in the function immediately on entry to the current function. This
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// eliminates the need for add/sub ESP brackets around call sites.
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//
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NumBytes += FFI->getMaxCallFrameSize();
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}
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// adjust stack pointer: ESP -= numbytes
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MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
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MBBI = 1+MBB.insert(MBBI, MI);
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if (NumBytes) {
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// adjust stack pointer: ESP -= numbytes
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MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
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MBBI = 1+MBB.insert(MBBI, MI);
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}
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}
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void X86RegisterInfo::emitEpilogue(MachineBasicBlock &MBB,
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unsigned numBytes) const {
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void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const FunctionFrameInfo *FFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = MBB.end()-1;
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MachineInstr *MI;
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assert((*MBBI)->getOpcode() == X86::RET &&
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"Can only insert epilog into returning blocks");
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// insert LEAVE: mov ESP, EBP; pop EBP
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MBBI = 1+MBB.insert(MBBI, BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP));
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MBBI = 1+MBB.insert(MBBI, BuildMI(X86::POPr32, 1).addReg(X86::EBP));
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if (hasFP(MF)) {
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// Get the offset of the stack slot for the EBP register... which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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int EBPOffset = FFI->getObjectOffset(FFI->getObjectIndexEnd()-1);
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// mov ESP, EBP
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MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
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MBBI = 1+MBB.insert(MBBI, MI);
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// mov EBP, [ESP-<offset>]
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MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
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MBBI = 1+MBB.insert(MBBI, MI);
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} else {
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if (!hasSPAdjust(MF)) return;
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = FFI->getStackSize();
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NumBytes += FFI->getMaxCallFrameSize();
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if (NumBytes) { // adjust stack pointer back: ESP += numbytes
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MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
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MBBI = 1+MBB.insert(MBBI, MI);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Register Class Implementation Code
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// 8 Bit Integer Registers
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//
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namespace {
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const unsigned ByteRegClassRegs[] = {
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X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
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};
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TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
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ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
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//===----------------------------------------------------------------------===//
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// 16 Bit Integer Registers
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//
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const unsigned ShortRegClassRegs[] = {
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X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
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};
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struct R16CL : public TargetRegisterClass {
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R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // Don't allocate SP or BP
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else
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return end()-1; // Don't allocate SP
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}
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} X86ShortRegisterClassInstance;
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//===----------------------------------------------------------------------===//
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// 32 Bit Integer Registers
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//
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const unsigned IntRegClassRegs[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::EBX,
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X86::ESI, X86::EDI, X86::EBP, X86::ESP
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};
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struct R32CL : public TargetRegisterClass {
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R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // Don't allocate ESP or EBP
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else
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return end()-1; // Don't allocate ESP
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}
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} X86IntRegisterClassInstance;
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//===----------------------------------------------------------------------===//
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// Pseudo Floating Point Registers
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//
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const unsigned PFPRegClassRegs[] = {
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#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
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#include "X86RegisterInfo.def"
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};
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TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
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PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
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//===----------------------------------------------------------------------===//
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// Register class array...
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//
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const TargetRegisterClass * const X86RegClasses[] = {
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&X86ByteRegisterClassInstance,
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&X86ShortRegisterClassInstance,
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&X86IntRegisterClassInstance,
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&X86FPRegisterClassInstance,
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};
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}
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// Create static lists to contain register alias sets...
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#define ALIASLIST(NAME, ...) \
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static const unsigned NAME[] = { __VA_ARGS__ };
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#include "X86RegisterInfo.def"
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// X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
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// descriptors
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//
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static const MRegisterDesc X86Regs[] = {
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#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
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{ NAME, ALIAS_SET, FLAGS, TSFLAGS },
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#include "X86RegisterInfo.def"
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};
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X86RegisterInfo::X86RegisterInfo()
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: MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
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X86RegClasses,
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X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
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X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
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}
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const TargetRegisterClass*
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X86RegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getPrimitiveID()) {
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID: return &X86ByteRegisterClassInstance;
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case Type::ShortTyID:
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case Type::UShortTyID: return &X86ShortRegisterClassInstance;
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case Type::LongTyID: // FIXME: Longs are not handled yet!
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case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus!
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &X86IntRegisterClassInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &X86FPRegisterClassInstance;
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}
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}
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