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[mips][microMIPS] Implement movep instruction

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Differential Revision: http://reviews.llvm.org/D7465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
2015-02-10 16:36:20 +00:00
parent b8ee890901
commit 3c53772000
11 changed files with 250 additions and 0 deletions
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65
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@@ -114,6 +114,11 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@@ -439,6 +444,10 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
namespace llvm {
extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
TheMips64elTarget;
@@ -1005,6 +1014,17 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@@ -1835,6 +1855,51 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
switch (RegPair) {
default:
return MCDisassembler::Fail;
case 0:
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
break;
case 1:
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
case 2:
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
case 3:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::S5));
break;
case 4:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::S6));
break;
case 5:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A1));
break;
case 6:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A2));
break;
case 7:
Inst.addOperand(MCOperand::CreateReg(Mips::A0));
Inst.addOperand(MCOperand::CreateReg(Mips::A3));
break;
}
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));