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When using inline asm constraints representing

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non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2012-05-07 03:13:16 +00:00
parent f09769067f
commit 3ccbd47ecb
1 changed files with 1 additions and 1 deletions
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2
lib/Target/Mips/MipsISelLowering.cpp
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@ -3054,7 +3054,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
case 'y': // Same as 'r'. Exists for compatibility.
case 'r':
if (VT == MVT::i32)
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
return std::make_pair(0U, &Mips::CPURegsRegClass);
assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair(0U, &Mips::CPU64RegsRegClass);