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Added sextld + zextld DAG nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24703 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -150,6 +150,12 @@ def SDTStore : SDTypeProfile<0, 2, [ // store
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SDTCisPtrTy<1>
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]>;
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def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>,
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SDTCisVTSmallerThanOp<3, 0>
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]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Properties.
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//
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@ -173,6 +179,7 @@ class SDNode<string opcode, SDTypeProfile typeprof,
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def set;
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def node;
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def srcvalue;
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def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
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@ -245,6 +252,11 @@ def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
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def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
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def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
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// Do not use sextld and zextld directly. Use sextload and zextload (see
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// below) which pass in a dummy srcvalue node which tblgen will skip over.
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def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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@ -311,6 +323,11 @@ def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
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def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
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def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
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// extending load fragments.
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def sextload : PatFrag<(ops node:$ptr, node:$vt),
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(sextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def zextload : PatFrag<(ops node:$ptr, node:$vt),
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(zextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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// setcc convenience fragments.
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def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
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