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Fix tests not to depend on specific regalloc or instruction order.

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They were failing with -mcpu=atom.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192890 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-10-17 12:41:05 +00:00
parent 071aed9422
commit 3d5694dca9
2 changed files with 4 additions and 4 deletions
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4
test/CodeGen/X86/widen_conv-2.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: cwtl
; CHECK: cwtl
; CHECK: {{cwtl|movswl}}
; CHECK: {{cwtl|movswl}}
; sign extension v2i32 to v2i16

4
test/CodeGen/X86/x86-64-tls-1.ll
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@ -3,8 +3,8 @@
define i64 @z() nounwind {
; FIXME: The codegen here is primitive at best and could be much better.
; The add and the moves can be folded together.
; CHECK: movq $tm_nest_level@TPOFF, %rcx
; CHECK: movq %fs:0, %rax
; CHECK-DAG: movq $tm_nest_level@TPOFF, %rcx
; CHECK-DAG: movq %fs:0, %rax
; CHECK: addl %ecx, %eax
ret i64 and (i64 ptrtoint (i32* @tm_nest_level to i64), i64 100)
}