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Move REG_SEQUENCE removal to 2addr pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103109 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,6 +40,7 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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@ -77,6 +78,10 @@ namespace {
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// registers from virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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/// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
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/// during the initial walk of the machine function.
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SmallVector<MachineInstr*, 16> RegSequences;
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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@ -123,6 +128,10 @@ namespace {
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
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/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
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/// sub-register references of the register defined by REG_SEQUENCE.
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bool EliminateRegSequences();
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
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@ -929,6 +938,10 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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continue;
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}
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// Remember REG_SEQUENCE instructions, we'll deal with them later.
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if (mi->isRegSequence())
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RegSequences.push_back(&*mi);
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const TargetInstrDesc &TID = mi->getDesc();
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bool FirstTied = true;
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@ -1110,5 +1123,60 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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VReg = ReMatRegs.find_next(VReg);
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}
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// Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
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// SSA form. It's now safe to de-SSA.
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MadeChange |= EliminateRegSequences();
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return MadeChange;
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}
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static void UpdateRegSequenceSrcs(unsigned SrcReg,
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unsigned DstReg, unsigned SrcIdx,
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MachineRegisterInfo *MRI) {
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for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
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UE = MRI->reg_end(); RI != UE; ) {
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MachineOperand &MO = RI.getOperand();
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++RI;
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MO.setReg(DstReg);
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MO.setSubReg(SrcIdx);
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}
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}
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/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
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/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
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/// sub-register references of the register defined by REG_SEQUENCE. e.g.
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///
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/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
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/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
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/// =>
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/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
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bool TwoAddressInstructionPass::EliminateRegSequences() {
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if (RegSequences.empty())
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return false;
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for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
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MachineInstr *MI = RegSequences[i];
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unsigned DstReg = MI->getOperand(0).getReg();
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if (MI->getOperand(0).getSubReg() ||
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TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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!(MI->getNumOperands() & 1)) {
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DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
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llvm_unreachable(0);
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}
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for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
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unsigned SrcReg = MI->getOperand(i).getReg();
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if (MI->getOperand(i).getSubReg() ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
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llvm_unreachable(0);
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}
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unsigned SrcIdx = MI->getOperand(i+1).getImm();
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UpdateRegSequenceSrcs(SrcReg, DstReg, SrcIdx, MRI);
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}
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DEBUG(dbgs() << "Eliminated: " << *MI);
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MI->eraseFromParent();
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}
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return true;
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}
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