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Changed the liveness tracking in the RegisterScavenger

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to use register units instead of registers.

reviewed by Jakob Stoklund Olesen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pedro Artigas
2014-08-04 23:07:49 +00:00
parent db3ce56a58
commit 3da024594f
8 changed files with 116 additions and 114 deletions
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124
lib/CodeGen/RegisterScavenging.cpp
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@@ -31,18 +31,10 @@ using namespace llvm;
#define DEBUG_TYPE "reg-scavenging"
/// setUsed - Set the register and its sub-registers as being used.
void RegScavenger::setUsed(unsigned Reg) {
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
RegsAvailable.reset(*SubRegs);
}
bool RegScavenger::isAliasUsed(unsigned Reg) const {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
if (isUsed(*AI, *AI == Reg))
return true;
return false;
/// setUsed - Set the register units of this register as used.
void RegScavenger::setRegUsed(unsigned Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
RegUnitsAvailable.reset(*RUI);
}
void RegScavenger::initRegState() {
@@ -52,8 +44,8 @@ void RegScavenger::initRegState() {
I->Restore = nullptr;
}
// All registers started out unused.
RegsAvailable.set();
// All register units start out unused.
RegUnitsAvailable.set();
if (!MBB)
return;
@@ -61,12 +53,12 @@ void RegScavenger::initRegState() {
// Live-in registers are in use.
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I)
setUsed(*I);
setRegUsed(*I);
// Pristine CSRs are also unavailable.
BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
for (int I = PR.find_first(); I>0; I = PR.find_next(I))
setUsed(I);
setRegUsed(I);
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
@@ -76,7 +68,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
TRI = TM.getSubtargetImpl()->getRegisterInfo();
MRI = &MF.getRegInfo();
assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
"Target changed?");
// It is not possible to use the register scavenger after late optimization
@@ -86,17 +78,11 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
// Self-initialize.
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
KillRegs.resize(NumPhysRegs);
DefRegs.resize(NumPhysRegs);
// Create callee-saved registers bitvector.
CalleeSavedRegs.resize(NumPhysRegs);
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
if (CSRegs != nullptr)
for (unsigned i = 0; CSRegs[i]; ++i)
CalleeSavedRegs.set(CSRegs[i]);
NumRegUnits = TRI->getNumRegUnits();
RegUnitsAvailable.resize(NumRegUnits);
KillRegUnits.resize(NumRegUnits);
DefRegUnits.resize(NumRegUnits);
TmpRegUnits.resize(NumRegUnits);
}
MBB = mbb;
@@ -105,10 +91,9 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
Tracking = false;
}
void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
BV.set(*SubRegs);
void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.set(*RUI);
}
void RegScavenger::determineKillsAndDefs() {
@@ -123,12 +108,25 @@ void RegScavenger::determineKillsAndDefs() {
// predicated, conservatively assume "kill" markers do not actually kill the
// register. Similarly ignores "dead" markers.
bool isPred = TII->isPredicated(MI);
KillRegs.reset();
DefRegs.reset();
KillRegUnits.reset();
DefRegUnits.reset();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegMask())
(isPred ? DefRegs : KillRegs).setBitsNotInMask(MO.getRegMask());
if (MO.isRegMask()) {
TmpRegUnits.clear();
for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
if (MO.clobbersPhysReg(*RURI)) {
TmpRegUnits.set(RU);
break;
}
}
}
// Apply the mask.
(isPred ? DefRegUnits : KillRegUnits) |= TmpRegUnits;
}
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
@@ -140,13 +138,13 @@ void RegScavenger::determineKillsAndDefs() {
if (MO.isUndef())
continue;
if (!isPred && MO.isKill())
addRegWithSubRegs(KillRegs, Reg);
addRegUnits(KillRegUnits, Reg);
} else {
assert(MO.isDef());
if (!isPred && MO.isDead())
addRegWithSubRegs(KillRegs, Reg);
addRegUnits(KillRegUnits, Reg);
else
addRegWithSubRegs(DefRegs, Reg);
addRegUnits(DefRegUnits, Reg);
}
}
}
@@ -159,8 +157,8 @@ void RegScavenger::unprocess() {
determineKillsAndDefs();
// Commit the changes.
setUsed(KillRegs);
setUnused(DefRegs);
setUsed(KillRegUnits);
setUnused(DefRegUnits);
}
if (MBBI == MBB->begin()) {
@@ -209,7 +207,7 @@ void RegScavenger::forward() {
if (MO.isUse()) {
if (MO.isUndef())
continue;
if (!isUsed(Reg)) {
if (!isRegUsed(Reg)) {
// Check if it's partial live: e.g.
// D0 = insert_subreg D0<undef>, S0
// ... D0
@@ -220,15 +218,23 @@ void RegScavenger::forward() {
// insert_subreg around causes both correctness and performance issues.
bool SubUsed = false;
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
if (isUsed(*SubRegs)) {
if (isRegUsed(*SubRegs)) {
SubUsed = true;
break;
}
if (!SubUsed) {
bool SuperUsed = false;
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
if (isRegUsed(*SR)) {
SuperUsed = true;
break;
}
}
if (!SubUsed && !SuperUsed) {
MBB->getParent()->verify(nullptr, "In Register Scavenger");
llvm_unreachable("Using an undefined register!");
}
(void)SubUsed;
(void)SuperUsed;
}
} else {
assert(MO.isDef());
@@ -244,23 +250,23 @@ void RegScavenger::forward() {
#endif // NDEBUG
// Commit the changes.
setUnused(KillRegs);
setUsed(DefRegs);
setUnused(KillRegUnits);
setUsed(DefRegUnits);
}
void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
used = RegsAvailable;
used.flip();
if (includeReserved)
used |= MRI->getReservedRegs();
else
used.reset(MRI->getReservedRegs());
bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
if (includeReserved && isReserved(Reg))
return true;
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
if (!RegUnitsAvailable.test(*RUI))
return true;
return false;
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I)
if (!isAliasUsed(*I)) {
if (!isRegUsed(*I)) {
DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
"\n");
return *I;
@@ -274,13 +280,13 @@ BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
BitVector Mask(TRI->getNumRegs());
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I)
if (!isAliasUsed(*I))
if (!isRegUsed(*I))
Mask.set(*I);
return Mask;
}
/// findSurvivorReg - Return the candidate register that is unused for the
/// longest after StargMII. UseMI is set to the instruction where the search
/// longest after StartMII. UseMI is set to the instruction where the search
/// stopped.
///
/// No more than InstrLimit instructions are inspected.
@@ -376,9 +382,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
}
// Try to find a register that's unused if there is one, as then we won't
// have to spill. Search explicitly rather than masking out based on
// RegsAvailable, as RegsAvailable does not take aliases into account.
// That's what getRegsAvailable() is for.
// have to spill.
BitVector Available = getRegsAvailable(RC);
Available &= Candidates;
if (Available.any())
@@ -389,7 +393,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
// If we found an unused register there is no reason to spill it.
if (!isAliasUsed(SReg)) {
if (!isRegUsed(SReg)) {
DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
return SReg;
}