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Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-08-30 07:09:35 +00:00
parent e497906e87
commit 3daa5c29d4
2 changed files with 30 additions and 4 deletions
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3
test/MC/Disassembler/X86/simple-tests.txt
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@ -96,3 +96,6 @@
# CHECK: vcvtsd2si %xmm0, %rax # CHECK: vcvtsd2si %xmm0, %rax
0xc4 0xe1 0xfb 0x2d 0xc0 0xc4 0xe1 0xfb 0x2d 0xc0
# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax)
0xc4 0xe2 0x71 0x2f 0x00

31
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -623,20 +623,43 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
case X86Local::MRMDestReg: case X86Local::MRMDestReg:
// Operand 1 is a register operand in the R/M field. // Operand 1 is a register operand in the R/M field.
// Operand 2 is a register operand in the Reg/Opcode field. // Operand 2 is a register operand in the Reg/Opcode field.
// - In AVX, there is a register operand in the VEX.vvvv field here -
// Operand 3 (optional) is an immediate. // Operand 3 (optional) is an immediate.
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && if (HasVEX_4VPrefix)
"Unexpected number of operands for MRMDestRegFrm"); assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
"Unexpected number of operands for MRMDestRegFrm with VEX_4V");
else
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
"Unexpected number of operands for MRMDestRegFrm");
HANDLE_OPERAND(rmRegister) HANDLE_OPERAND(rmRegister)
if (HasVEX_4VPrefix)
// FIXME: In AVX, the register below becomes the one encoded
// in ModRMVEX and the one above the one in the VEX.VVVV field
HANDLE_OPERAND(vvvvRegister)
HANDLE_OPERAND(roRegister) HANDLE_OPERAND(roRegister)
HANDLE_OPTIONAL(immediate) HANDLE_OPTIONAL(immediate)
break; break;
case X86Local::MRMDestMem: case X86Local::MRMDestMem:
// Operand 1 is a memory operand (possibly SIB-extended) // Operand 1 is a memory operand (possibly SIB-extended)
// Operand 2 is a register operand in the Reg/Opcode field. // Operand 2 is a register operand in the Reg/Opcode field.
// - In AVX, there is a register operand in the VEX.vvvv field here -
// Operand 3 (optional) is an immediate. // Operand 3 (optional) is an immediate.
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && if (HasVEX_4VPrefix)
"Unexpected number of operands for MRMDestMemFrm"); assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
"Unexpected number of operands for MRMDestMemFrm with VEX_4V");
else
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
"Unexpected number of operands for MRMDestMemFrm");
HANDLE_OPERAND(memory) HANDLE_OPERAND(memory)
if (HasVEX_4VPrefix)
// FIXME: In AVX, the register below becomes the one encoded
// in ModRMVEX and the one above the one in the VEX.VVVV field
HANDLE_OPERAND(vvvvRegister)
HANDLE_OPERAND(roRegister) HANDLE_OPERAND(roRegister)
HANDLE_OPTIONAL(immediate) HANDLE_OPTIONAL(immediate)
break; break;