6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-02 07:32:52 +00:00
Code Issues Projects Releases Wiki Activity

Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-11 18:41:59 +00:00
parent 0fa5e053a9
commit 3dac0bec7e
3 changed files with 20 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -25,6 +25,16 @@ using namespace llvm;
#define GET_INSTRUCTION_NAME #define GET_INSTRUCTION_NAME
#include "ARMGenAsmWriter.inc" #include "ARMGenAsmWriter.inc"
/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
///
/// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
/// 32 as the immediate shouldbe within the range 1-32.
static unsigned translateShiftImm(unsigned imm) {
if (imm == 0)
return 32;
return imm;
}
StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const { StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
return getInstructionName(Opcode); return getInstructionName(Opcode);
} }
@ -72,7 +82,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
return; return;
O << ", #" << ARM_AM::getSORegOffset(MO2.getImm()); O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
return; return;
} }
@ -211,7 +221,7 @@ void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
O << ", " << ARM_AM::getShiftOpcStr(ShOpc); O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (ShOpc == ARM_AM::rrx) if (ShOpc == ARM_AM::rrx)
return; return;
O << " #" << ARM_AM::getSORegOffset(MO2.getImm()); O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
} }
@ -722,7 +732,7 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
O << ", " << ARM_AM::getShiftOpcStr(ShOpc); O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
if (ShOpc != ARM_AM::rrx) if (ShOpc != ARM_AM::rrx)
O << " #" << ARM_AM::getSORegOffset(MO2.getImm()); O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
} }
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,

5
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -1032,7 +1032,10 @@ getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
// Encode shift_imm bit[11:7]. // Encode shift_imm bit[11:7].
Binary |= SBits << 4; Binary |= SBits << 4;
return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
assert(Offset && "Offset must be in range 1-32!");
if (Offset == 32) Offset = 0;
return Binary | (Offset << 7);
} }

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -302,3 +302,6 @@
# CHECK: nop # CHECK: nop
0x00 0xf0 0x20 0xe3 0x00 0xf0 0x20 0xe3
# CHECK: andeq r0, r0, r0, lsr #32
0x20 0x00 0x00 0x00