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Move all operand definitions into HexagonOperands.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169213 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14,59 +14,6 @@
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include "HexagonInstrFormats.td"
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include "HexagonOperands.td"
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// Addressing modes.
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def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
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def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
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def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
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def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
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def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
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def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
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def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
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def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
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// Address operands.
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def MEMrr : Operand<i32> {
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let PrintMethod = "printMEMrrOperand";
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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// Address operands
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def MEMri : Operand<i32> {
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let PrintMethod = "printMEMriOperand";
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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def MEMri_s11_2 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
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let PrintMethod = "printMEMriOperand";
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let MIOperandInfo = (ops IntRegs, s11Imm);
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}
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def FrameIndex : Operand<i32> {
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let PrintMethod = "printFrameIndexOperand";
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let MIOperandInfo = (ops IntRegs, s11Imm);
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}
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let PrintMethod = "printGlobalOperand" in
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def globaladdress : Operand<i32>;
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let PrintMethod = "printJumpTable" in
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def jumptablebase : Operand<i32>;
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def bblabel : Operand<i32>;
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def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
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def symbolHi32 : Operand<i32> {
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let PrintMethod = "printSymbolHi";
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}
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def symbolLo32 : Operand<i32> {
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let PrintMethod = "printSymbolLo";
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}
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// Multi-class for logical operators.
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multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
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def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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@ -799,3 +799,60 @@ def u6_3ExtPred : PatLeaf<(i32 imm), [{
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return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 8) == 0);
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}
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}]>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
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def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
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def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
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def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
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def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
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def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
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def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
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def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
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// Address operands.
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def MEMrr : Operand<i32> {
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let PrintMethod = "printMEMrrOperand";
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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def MEMri : Operand<i32> {
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let PrintMethod = "printMEMriOperand";
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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def MEMri_s11_2 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
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let PrintMethod = "printMEMriOperand";
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let MIOperandInfo = (ops IntRegs, s11Imm);
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}
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def FrameIndex : Operand<i32> {
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let PrintMethod = "printFrameIndexOperand";
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let MIOperandInfo = (ops IntRegs, s11Imm);
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}
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let PrintMethod = "printGlobalOperand" in {
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def globaladdress : Operand<i32>;
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def globaladdressExt : Operand<i32>;
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}
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let PrintMethod = "printJumpTable" in
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def jumptablebase : Operand<i32>;
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def brtarget : Operand<OtherVT>;
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def brtargetExt : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def bblabel : Operand<i32>;
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def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf , [], "BasicBlockSDNode">;
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def symbolHi32 : Operand<i32> {
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let PrintMethod = "printSymbolHi";
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}
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def symbolLo32 : Operand<i32> {
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let PrintMethod = "printSymbolLo";
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}
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