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Remove some obsolete interfaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
060054b9d9
commit
3dc38d26fb
@ -25,8 +25,6 @@ class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetInstrDescriptor;
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class TargetJITInfo;
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class TargetJITInfo;
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class TargetLowering;
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class TargetLowering;
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class TargetSchedInfo;
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class SparcV9RegInfo;
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class TargetFrameInfo;
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class TargetFrameInfo;
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class MachineCodeEmitter;
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class MachineCodeEmitter;
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class MRegisterInfo;
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class MRegisterInfo;
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@ -133,10 +131,6 @@ public:
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return InstrItineraryData();
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return InstrItineraryData();
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}
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}
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// These are deprecated interfaces.
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virtual const TargetSchedInfo *getSchedInfo() const { return 0; }
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virtual const SparcV9RegInfo *getRegInfo() const { return 0; }
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/// getRelocationModel - Returns the code generation relocation model. The
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/// getRelocationModel - Returns the code generation relocation model. The
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/// choices are static, PIC, and dynamic-no-pic, and target default.
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/// choices are static, PIC, and dynamic-no-pic, and target default.
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static Reloc::Model getRelocationModel();
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static Reloc::Model getRelocationModel();
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@ -1,292 +0,0 @@
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//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine to the instruction scheduler.
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//
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// NOTE: This file is currently sparc V9 specific.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
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#define LLVM_TARGET_TARGETSCHEDINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/hash_map"
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#include <string>
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namespace llvm {
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typedef long long CycleCount_t;
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static const CycleCount_t HUGE_LATENCY = ~((long long) 1 << (sizeof(CycleCount_t)-2));
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static const CycleCount_t INVALID_LATENCY = -HUGE_LATENCY;
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//---------------------------------------------------------------------------
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// class MachineResource
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// class CPUResource
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//
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// Purpose:
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// Representation of a single machine resource used in specifying
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// resource usages of machine instructions for scheduling.
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//---------------------------------------------------------------------------
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typedef unsigned resourceId_t;
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struct CPUResource {
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const std::string rname;
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resourceId_t rid;
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int maxNumUsers; // MAXINT if no restriction
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CPUResource(const std::string& resourceName, int maxUsers);
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static CPUResource* getCPUResource(resourceId_t id);
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private:
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static resourceId_t nextId;
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};
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//---------------------------------------------------------------------------
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// struct InstrClassRUsage
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// struct InstrRUsageDelta
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// struct InstrIssueDelta
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// struct InstrRUsage
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//
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// Purpose:
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// The first three are structures used to specify machine resource
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// usages for each instruction in a machine description file:
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// InstrClassRUsage : resource usages common to all instrs. in a class
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// InstrRUsageDelta : add/delete resource usage for individual instrs.
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// InstrIssueDelta : add/delete instr. issue info for individual instrs
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//
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// The last one (InstrRUsage) is the internal representation of
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// instruction resource usage constructed from the above three.
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//---------------------------------------------------------------------------
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const int MAX_NUM_SLOTS = 32;
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const int MAX_NUM_CYCLES = 32;
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struct InstrClassRUsage {
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InstrSchedClass schedClass;
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int totCycles;
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// Issue restrictions common to instructions in this class
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unsigned maxNumIssue;
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bool isSingleIssue;
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bool breaksGroup;
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CycleCount_t numBubbles;
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// Feasible slots to use for instructions in this class.
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// The size of vector S[] is `numSlots'.
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unsigned numSlots;
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unsigned feasibleSlots[MAX_NUM_SLOTS];
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// Resource usages common to instructions in this class.
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// The size of vector V[] is `numRUEntries'.
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unsigned numRUEntries;
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struct {
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resourceId_t resourceId;
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unsigned startCycle;
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int numCycles;
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} V[MAX_NUM_CYCLES];
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};
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struct InstrRUsageDelta {
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MachineOpCode opCode;
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resourceId_t resourceId;
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unsigned startCycle;
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int numCycles;
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};
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// Specify instruction issue restrictions for individual instructions
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// that differ from the common rules for the class.
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//
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struct InstrIssueDelta {
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MachineOpCode opCode;
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bool isSingleIssue;
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bool breaksGroup;
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CycleCount_t numBubbles;
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};
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struct InstrRUsage {
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bool sameAsClass;
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// Issue restrictions for this instruction
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bool isSingleIssue;
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bool breaksGroup;
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CycleCount_t numBubbles;
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// Feasible slots to use for this instruction.
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std::vector<bool> feasibleSlots;
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// Resource usages for this instruction, with one resource vector per cycle.
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CycleCount_t numCycles;
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std::vector<std::vector<resourceId_t> > resourcesByCycle;
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private:
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// Conveniences for initializing this structure
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void setTo(const InstrClassRUsage& classRU);
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void addIssueDelta(const InstrIssueDelta& delta) {
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sameAsClass = false;
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isSingleIssue = delta.isSingleIssue;
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breaksGroup = delta.breaksGroup;
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numBubbles = delta.numBubbles;
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}
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void addUsageDelta(const InstrRUsageDelta& delta);
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void setMaxSlots(int maxNumSlots) {
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feasibleSlots.resize(maxNumSlots);
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}
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friend class TargetSchedInfo; // give access to these functions
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};
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//---------------------------------------------------------------------------
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/// TargetSchedInfo - Common interface to machine information for
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/// instruction scheduling
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///
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class TargetSchedInfo {
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public:
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const TargetMachine& target;
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unsigned maxNumIssueTotal;
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int longestIssueConflict;
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protected:
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inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int) instrRUsages.size());
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return instrRUsages[opCode];
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}
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const InstrClassRUsage& getClassRUsage(const InstrSchedClass& sc) const {
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assert(sc < numSchedClasses);
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return classRUsages[sc];
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}
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private:
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TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
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public:
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TargetSchedInfo(const TargetMachine& tgt,
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int _numSchedClasses,
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const InstrClassRUsage* _classRUsages,
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const InstrRUsageDelta* _usageDeltas,
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const InstrIssueDelta* _issueDeltas,
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unsigned _numUsageDeltas,
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unsigned _numIssueDeltas);
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virtual ~TargetSchedInfo() {}
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inline const TargetInstrInfo& getInstrInfo() const {
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return *mii;
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}
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inline int getNumSchedClasses() const {
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return numSchedClasses;
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}
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inline unsigned getMaxNumIssueTotal() const {
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return maxNumIssueTotal;
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}
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inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
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assert(sc < numSchedClasses);
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return classRUsages[sc].maxNumIssue;
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}
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inline InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return getInstrInfo().getSchedClass(opCode);
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}
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inline bool instrCanUseSlot(MachineOpCode opCode,
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unsigned s) const {
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assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
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return getInstrRUsage(opCode).feasibleSlots[s];
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}
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inline int getLongestIssueConflict() const {
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return longestIssueConflict;
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}
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inline int getMinIssueGap(MachineOpCode fromOp,
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MachineOpCode toOp) const {
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assert(fromOp < (int) issueGaps.size());
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const std::vector<int>& toGaps = issueGaps[fromOp];
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return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
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}
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inline const std::vector<MachineOpCode>&
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getConflictList(MachineOpCode opCode) const {
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assert(opCode < (int) conflictLists.size());
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return conflictLists[opCode];
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}
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inline bool isSingleIssue(MachineOpCode opCode) const {
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return getInstrRUsage(opCode).isSingleIssue;
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}
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inline bool breaksIssueGroup(MachineOpCode opCode) const {
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return getInstrRUsage(opCode).breaksGroup;
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}
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inline unsigned numBubblesAfter(MachineOpCode opCode) const {
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return getInstrRUsage(opCode).numBubbles;
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}
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inline unsigned getCPUResourceNum(int rd)const{
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for(unsigned i=0;i<resourceNumVector.size();i++){
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if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
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}
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assert( 0&&"resource not found");
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return 0;
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}
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protected:
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virtual void initializeResources();
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private:
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void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
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void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);
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void setGap(int gap, MachineOpCode fromOp, MachineOpCode toOp) {
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std::vector<int>& toGaps = issueGaps[fromOp];
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if (toOp >= (int) toGaps.size())
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toGaps.resize(toOp+1);
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toGaps[toOp] = gap;
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}
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public:
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std::vector<std::pair<int,int> > resourceNumVector;
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protected:
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unsigned numSchedClasses;
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const TargetInstrInfo* mii;
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const InstrClassRUsage* classRUsages; // raw array by sclass
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const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
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const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
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unsigned numUsageDeltas;
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unsigned numIssueDeltas;
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std::vector<InstrRUsage> instrRUsages; // indexed by opcode
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std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
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std::vector<std::vector<MachineOpCode> >
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conflictLists; // indexed by [opcode]
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friend class ModuloSchedulingPass;
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friend class ModuloSchedulingSBPass;
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friend class MSSchedule;
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friend class MSScheduleSB;
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friend class MSchedGraphSB;
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};
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} // End llvm namespace
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#endif
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