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Codegen shufflevector as VVECTOR_SHUFFLE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27529 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1447,6 +1447,12 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
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AddToWorkList(XORNode.Val);
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return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
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}
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// Simplify the expression using non-local knowledge.
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if (!MVT::isVector(VT) &&
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SimplifyDemandedBits(SDOperand(N, 0)))
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return SDOperand();
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return SDOperand();
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}
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@ -2044,8 +2050,10 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
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// type, convert each element. This handles FP<->INT cases.
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if (SrcBitSize == DstBitSize) {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i)
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for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
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Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
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AddToWorkList(Ops.back().Val);
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}
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Ops.push_back(*(BV->op_end()-2)); // Add num elements.
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Ops.push_back(DAG.getValueType(DstEltVT));
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return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
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@ -2635,6 +2643,7 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
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UnOps.push_back(NumElts);
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UnOps.push_back(EltType);
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Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
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AddToWorkList(Ops.back().Val);
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}
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Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
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Ops.push_back(NumElts);
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@ -2690,6 +2699,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
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MappedOps);
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AddToWorkList(ShufMask.Val);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
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N->getOperand(0),
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DAG.getNode(ISD::UNDEF, N->getValueType(0)),
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@ -2755,6 +2765,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
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RHSOp.getOpcode() != ISD::ConstantFP))
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break;
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Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
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AddToWorkList(Ops.back().Val);
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assert((Ops.back().getOpcode() == ISD::UNDEF ||
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Ops.back().getOpcode() == ISD::Constant ||
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Ops.back().getOpcode() == ISD::ConstantFP) &&
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@ -516,7 +516,7 @@ public:
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void visitExtractElement(User &I);
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void visitInsertElement(User &I);
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void visitShuffleVector(User &I) { assert(0 && "ShuffleVector not impl!"); }
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void visitShuffleVector(User &I);
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void visitGetElementPtr(User &I);
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void visitCast(User &I);
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@ -1076,6 +1076,18 @@ void SelectionDAGLowering::visitExtractElement(User &I) {
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TLI.getValueType(I.getType()), InVec, InIdx));
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}
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void SelectionDAGLowering::visitShuffleVector(User &I) {
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SDOperand V1 = getValue(I.getOperand(0));
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SDOperand V2 = getValue(I.getOperand(1));
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SDOperand Mask = getValue(I.getOperand(2));
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SDOperand Num = *(V1.Val->op_end()-2);
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SDOperand Typ = *(V2.Val->op_end()-1);
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setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
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V1, V2, Mask, Num, Typ));
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}
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void SelectionDAGLowering::visitGetElementPtr(User &I) {
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SDOperand N = getValue(I.getOperand(0));
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const Type *Ty = I.getOperand(0)->getType();
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