6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-09 10:31:14 +00:00
Code Issues Projects Releases Wiki Activity

implement a couple of simple shift foldings.

Browse Source 
e.g.  (X & 7) >> 3   -> 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22774 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-12 23:54:58 +00:00
parent cf083e312c
commit 3e27b1f5c4
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -993,6 +993,24 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
return getNode(ISD::UNDEF, N1.getValueType());
}
if (C2 == 0) return N1;
if (Opcode == ISD::SRA) {
// If the sign bit is known to be zero, switch this to a SRL.
if (MaskedValueIsZero(N1,
1ULL << MVT::getSizeInBits(N1.getValueType())-1,
TLI))
return getNode(ISD::SRL, N1.getValueType(), N1, N2);
} else {
// If the part left over is known to be zero, the whole thing is zero.
uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType()));
if (Opcode == ISD::SRL) {
if (MaskedValueIsZero(N1, TypeMask << C2, TLI))
return getConstant(0, N1.getValueType());
} else if (Opcode == ISD::SHL) {
if (MaskedValueIsZero(N1, TypeMask >> C2, TLI))
return getConstant(0, N1.getValueType());
}
}
if (Opcode == ISD::SHL && N1.getNumOperands() == 2)
if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {