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This may be overconservative, but it lets the new cfe compile

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2006-04-06 23:18:45 +00:00
parent 1c80103016
commit 3e2c745d0d
1 changed files with 2 additions and 1 deletions
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3
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -571,7 +571,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
GlobalValue *GV = GSDN->getGlobal(); GlobalValue *GV = GSDN->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) { // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);