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add patterns to the addi/addis/mulli etc instructions. Define predicates

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for matching signed 16-bit and shifted 16-bit ppc immediates


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-08 17:33:10 +00:00
parent d1cdc7028c
commit 3e63ead49b
2 changed files with 52 additions and 16 deletions
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15
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -81,7 +81,9 @@ class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
} }
// 1.7.4 D-Form // 1.7.4 D-Form
class DForm_base<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr>{ class DForm_base<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
: I<opcode, OL, asmstr> {
let Pattern = pattern;
bits<5> A; bits<5> A;
bits<5> B; bits<5> B;
bits<16> C; bits<16> C;
@ -91,7 +93,8 @@ class DForm_base<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr>{
let Inst{16-31} = C; let Inst{16-31} = C;
} }
class DForm_1<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> { class DForm_1<bits<6> opcode, dag OL, string asmstr>
: I<opcode, OL, asmstr> {
bits<5> A; bits<5> A;
bits<16> C; bits<16> C;
bits<5> B; bits<5> B;
@ -101,14 +104,16 @@ class DForm_1<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
let Inst{16-31} = C; let Inst{16-31} = C;
} }
class DForm_2<bits<6> opcode, dag OL, string asmstr> class DForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
: DForm_base<opcode, OL, asmstr>; : DForm_base<opcode, OL, asmstr, pattern>;
class DForm_2_r0<bits<6> opcode, dag OL, string asmstr> class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
: I<opcode, OL, asmstr> { : I<opcode, OL, asmstr> {
bits<5> A; bits<5> A;
bits<16> B; bits<16> B;
let Pattern = pattern;
let Inst{6-10} = A; let Inst{6-10} = A;
let Inst{11-15} = 0; let Inst{11-15} = 0;
let Inst{16-31} = B; let Inst{16-31} = B;

53
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -40,12 +40,17 @@ def ctlz : SDNode<"ISD::CTLZ">;
/// PatFrag - Represents a pattern fragment. This can match something on the /// PatFrag - Represents a pattern fragment. This can match something on the
/// DAG, frame a single node to multiply nested other fragments. /// DAG, frame a single node to multiply nested other fragments.
/// ///
class PatFrag<dag ops, dag frag, code pred = [{}]> { class PatFrag<dag ops, dag frag, code pred = [{}], code xform = [{}]> {
dag Operands = ops; dag Operands = ops;
dag Fragment = frag; dag Fragment = frag;
code Predicate = pred; code Predicate = pred;
code OperandTransform = xform;
} }
class PatLeaf<dag frag, code pred = [{}]> : PatFrag<(ops), frag, pred>;
// PatLeaf's are pattern fragments that have no operands. This is just a helper
// to define immediates and other common things concisely.
class PatLeaf<dag frag, code pred = [{}], code xform = [{}]>
: PatFrag<(ops), frag, pred, xform>;
// Leaf fragments. // Leaf fragments.
@ -60,6 +65,23 @@ def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>; def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
// PowerPC-Specific predicates.
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
return (int)N->getValue() == (short)N->getValue();
}]>;
def imm16Shifted : PatLeaf<(imm), [{
// imm16Shifted predicate - True if only bits in the top 16-bits of the
// immediate are set. Used by instructions like 'addis'.
return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
}], [{
// Transformation predicate: shift the immediate value down into the low bits.
return getI32Imm((unsigned)N->getValue() >> 16);
}]>;
class isPPC64 { bit PPC64 = 1; } class isPPC64 { bit PPC64 = 1; }
class isVMX { bit VMX = 1; } class isVMX { bit VMX = 1; }
class isDOT { class isDOT {
@ -177,23 +199,32 @@ def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
"lwzu $rD, $disp($rA)">; "lwzu $rD, $disp($rA)">;
} }
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"addi $rD, $rA, $imm">; "addi $rD, $rA, $imm",
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"addic $rD, $rA, $imm">; "addic $rD, $rA, $imm",
[]>;
def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"addic. $rD, $rA, $imm">; "addic. $rD, $rA, $imm",
[]>;
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
"addis $rD, $rA, $imm">; "addis $rD, $rA, $imm",
[(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
"la $rD, $sym($rA)">; "la $rD, $sym($rA)",
[]>;
def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"mulli $rD, $rA, $imm">; "mulli $rD, $rA, $imm",
[(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
"subfic $rD, $rA, $imm">; "subfic $rD, $rA, $imm",
[]>;
def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm), def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
"li $rD, $imm">; "li $rD, $imm",
[(set GPRC:$rD, immSExt16:$imm)]>;
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
"lis $rD, $imm">; "lis $rD, $imm",
[(set GPRC:$rD, imm16Shifted:$imm)]>;
let isStore = 1 in { let isStore = 1 in {
def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
"stmw $rS, $disp($rA)">; "stmw $rS, $disp($rA)">;