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[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
d65d2fde4e
commit
3e6758541b
@ -329,6 +329,9 @@ namespace llvm {
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SmallVector<ByValArgInfo, 2> ByValArgs;
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};
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protected:
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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@ -366,8 +369,6 @@ namespace llvm {
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
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bool IsSRA) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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@ -368,12 +368,8 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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}
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let Predicates = [NotFP64bit, HasStdEnc] in {
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def PseudoLDC1 : LW_FT<"", AFGR64Opnd, IIFLoad, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64Opnd, IIFStore, store>;
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}
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def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore>, LW_FM<0x3d>;
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def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
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}
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// Indexed loads and stores.
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@ -595,7 +591,7 @@ let AddedComplexity = 40 in {
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}
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def : LoadRegImmPat<PseudoLDC1, f64, load>;
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def : StoreRegImmPat<PseudoSDC1, f64>;
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def : LoadRegImmPat<LDC1, f64, load>;
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def : StoreRegImmPat<SDC1, f64>;
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}
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}
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@ -25,6 +25,11 @@ static cl::opt<bool>
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EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
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cl::desc("MIPS: Enable tail calls."), cl::init(false));
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static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
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cl::desc("Expand double precision loads and "
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"stores to their single precision "
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"counterparts"));
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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// Set up the register classes
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@ -129,6 +134,11 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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if (NoDPLoadStore) {
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setOperationAction(ISD::LOAD, MVT::f64, Custom);
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setOperationAction(ISD::STORE, MVT::f64, Custom);
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}
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computeRegisterProperties();
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}
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@ -168,6 +178,8 @@ MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
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SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch(Op.getOpcode()) {
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case ISD::LOAD: return lowerLOAD(Op, DAG);
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case ISD::STORE: return lowerSTORE(Op, DAG);
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case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
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case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
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case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
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@ -611,6 +623,68 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
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InternalLinkage, CLI, Callee, Chain);
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}
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SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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LoadSDNode &Nd = *cast<LoadSDNode>(Op);
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if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
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return MipsTargetLowering::lowerLOAD(Op, DAG);
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// Replace a double precision load with two i32 loads and a buildpair64.
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SDLoc DL(Op);
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SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
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EVT PtrVT = Ptr.getValueType();
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// i32 load from lower address.
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SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
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MachinePointerInfo(), Nd.isVolatile(),
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Nd.isNonTemporal(), Nd.isInvariant(),
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Nd.getAlignment());
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// i32 load from higher address.
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Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
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SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
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MachinePointerInfo(), Nd.isVolatile(),
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Nd.isNonTemporal(), Nd.isInvariant(),
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Nd.getAlignment());
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if (!Subtarget->isLittle())
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std::swap(Lo, Hi);
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SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
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SDValue Ops[2] = {BP, Hi.getValue(1)};
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return DAG.getMergeValues(Ops, 2, DL);
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}
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SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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StoreSDNode &Nd = *cast<StoreSDNode>(Op);
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if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
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return MipsTargetLowering::lowerSTORE(Op, DAG);
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// Replace a double precision store with two extractelement64s and i32 stores.
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SDLoc DL(Op);
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SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
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EVT PtrVT = Ptr.getValueType();
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SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
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Val, DAG.getConstant(0, MVT::i32));
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SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
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Val, DAG.getConstant(1, MVT::i32));
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if (!Subtarget->isLittle())
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std::swap(Lo, Hi);
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// i32 store to lower address.
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Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
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Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
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Nd.getTBAAInfo());
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// i32 store to higher address.
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Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
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return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
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Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
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Nd.getTBAAInfo());
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}
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SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
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bool HasLo, bool HasHi,
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SelectionDAG &DAG) const {
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@ -58,6 +58,9 @@ namespace llvm {
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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SelectionDAG &DAG) const;
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@ -24,11 +24,6 @@
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using namespace llvm;
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static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
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cl::desc("Expand double precision loads and "
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"stores to their single precision "
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"counterparts."));
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MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm,
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tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
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@ -294,12 +289,6 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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case Mips::ExtractElementF64_64:
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expandExtractElementF64(MBB, MI, true);
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break;
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case Mips::PseudoLDC1:
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expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
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break;
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case Mips::PseudoSDC1:
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expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1);
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break;
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case Mips::MIPSeh_return32:
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case Mips::MIPSeh_return64:
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expandEhReturn(MBB, MI);
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@ -484,56 +473,6 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
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.addReg(HiReg);
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}
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/// Add 4 to the displacement of operand MO.
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static void fixDisp(MachineOperand &MO) {
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switch (MO.getType()) {
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default:
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llvm_unreachable("Unhandled operand type.");
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case MachineOperand::MO_Immediate:
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MO.setImm(MO.getImm() + 4);
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break;
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_BlockAddress:
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case MachineOperand::MO_TargetIndex:
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case MachineOperand::MO_ExternalSymbol:
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MO.setOffset(MO.getOffset() + 4);
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break;
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}
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}
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void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned OpcD, unsigned OpcS) const {
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// If NoDPLoadStore is false, just change the opcode.
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if (!NoDPLoadStore) {
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genInstrWithNewOpc(OpcD, I);
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return;
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}
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// Expand a double precision FP load or store to two single precision
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// instructions.
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const TargetRegisterInfo &TRI = getRegisterInfo();
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const MachineOperand &ValReg = I->getOperand(0);
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unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_lo);
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unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_hi);
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if (!TM.getSubtarget<MipsSubtarget>().isLittle())
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std::swap(LoReg, HiReg);
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// Create an instruction which loads from or stores to the lower memory
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// address.
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MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
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MIB->getOperand(0).setReg(LoReg);
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// Create an instruction which loads from or stores to the higher memory
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// address.
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MIB = genInstrWithNewOpc(OpcS, I);
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MIB->getOperand(0).setReg(HiReg);
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fixDisp(MIB->getOperand(2));
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}
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void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// This pseudo instruction is generated as part of the lowering of
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@ -104,9 +104,6 @@ private:
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandDPLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, unsigned OpcD,
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unsigned OpcS) const;
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void expandEhReturn(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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@ -1,22 +1,31 @@
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; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=LE-PIC
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; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s -check-prefix=LE-PIC
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; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=LE-STATIC
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; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=BE-PIC
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK-LDC1-SDC1
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LDC1-SDC1
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@g0 = common global double 0.000000e+00, align 8
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; LE-PIC-LABEL: test_ldc1:
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; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
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; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
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; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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; LE-PIC-DAG: mtc1 $[[R0]], $f0
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; LE-PIC-DAG: mtc1 $[[R1]], $f1
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; LE-STATIC-LABEL: test_ldc1:
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; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
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; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
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; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
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; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
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; LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
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; LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
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; LE-STATIC-DAG: mtc1 $[[R1]], $f0
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; LE-STATIC-DAG: mtc1 $[[R3]], $f1
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; BE-PIC-LABEL: test_ldc1:
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; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
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; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
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; BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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; BE-PIC-DAG: mtc1 $[[R1]], $f0
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; BE-PIC-DAG: mtc1 $[[R0]], $f1
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; CHECK-LDC1-SDC1-LABEL: test_ldc1:
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; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
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@ -27,14 +36,22 @@ entry:
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}
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; LE-PIC-LABEL: test_sdc1:
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; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
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; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
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; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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; LE-STATIC-LABEL: test_sdc1:
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; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
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; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
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; LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
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; LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
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; LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
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; LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
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; BE-PIC-LABEL: test_sdc1:
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; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
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; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
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; BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
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; BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
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; CHECK-LDC1-SDC1-LABEL: test_sdc1:
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; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
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@ -43,3 +60,34 @@ entry:
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store double %a, double* @g0, align 8
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ret void
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}
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; CHECK-LE-PIC-DAG-LABEL: test_ldxc1:
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; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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; LE-PIC-DAG: mtc1 $[[R0]], $f0
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; LE-PIC-DAG: mtc1 $[[R1]], $f1
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; CHECK-LDC1-SDC1-LABEL: test_ldxc1:
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; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}}
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define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
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entry:
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%arrayidx = getelementptr inbounds double* %a, i32 %i
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%0 = load double* %arrayidx, align 8
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ret double %0
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}
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; LE-PIC-DAG-LABEL: test_sdxc1:
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; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
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; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
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; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
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; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
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; CHECK-LDC1-SDC1-LABEL: test_sdxc1:
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; CHECK-LDC1-SDC1: sdxc1 $f{{[0-9]+}}
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define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
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entry:
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%arrayidx = getelementptr inbounds double* %a, i32 %i
|
||||
store double %b, double* %arrayidx, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user