mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-29 10:32:47 +00:00
This patch adds X86 instruction itineraries for non-pseudo opcodes in
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Preston Gurd
parent
8118c94a55
commit
3e99b715d1
@ -153,7 +153,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, isCodeGenOnly = 1 in {
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def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR32:$addr)]>;
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[(X86ehret GR32:$addr)], IIC_RET>;
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}
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@ -161,7 +161,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, isCodeGenOnly = 1 in {
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def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR64:$addr)]>;
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[(X86ehret GR64:$addr)], IIC_RET>;
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}
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@ -193,7 +193,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
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let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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isCodeGenOnly = 1 in {
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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[(set GR8:$dst, 0)]>;
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[(set GR8:$dst, 0)], IIC_ALU_NONMEM>;
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// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
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// encoding and avoids a partial-register update sometimes, but doing so
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@ -202,11 +202,11 @@ def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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// to an MCInst.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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[(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
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// FIXME: Set encoding to pseudo.
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, 0)]>;
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[(set GR32:$dst, 0)], IIC_ALU_NONMEM>;
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}
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// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
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@ -218,7 +218,7 @@ def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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let Defs = [EFLAGS], isCodeGenOnly=1,
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AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
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[(set GR64:$dst, 0)]>;
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[(set GR64:$dst, 0)], IIC_ALU_NONMEM>;
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// Materialize i64 constant where top 32-bits are zero. This could theoretically
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// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
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@ -226,7 +226,8 @@ def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
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let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
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isCodeGenOnly = 1 in
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def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
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"", [(set GR64:$dst, i64immZExt32:$src)]>;
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"", [(set GR64:$dst, i64immZExt32:$src)],
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IIC_ALU_NONMEM>;
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// Use sbb to materialize carry bit.
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let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
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@ -236,14 +237,18 @@ let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
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// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
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// X86CodeEmitter.
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def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
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[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
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IIC_ALU_NONMEM>;
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def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
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[(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
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[(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
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IIC_ALU_NONMEM>,
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OpSize;
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def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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[(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
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IIC_ALU_NONMEM>;
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def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
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[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
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IIC_ALU_NONMEM>;
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} // isCodeGenOnly
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@ -297,32 +302,32 @@ def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
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//
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let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
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def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
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[(X86rep_movs i8)]>, REP;
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[(X86rep_movs i8)], IIC_REP_MOVS>, REP;
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def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
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[(X86rep_movs i16)]>, REP, OpSize;
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[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize;
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def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
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[(X86rep_movs i32)]>, REP;
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[(X86rep_movs i32)], IIC_REP_MOVS>, REP;
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}
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let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
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def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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[(X86rep_movs i64)]>, REP;
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[(X86rep_movs i64)], IIC_REP_MOVS>, REP;
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// FIXME: Should use "(X86rep_stos AL)" as the pattern.
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let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
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def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
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[(X86rep_stos i8)]>, REP;
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[(X86rep_stos i8)], IIC_REP_STOS>, REP;
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let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
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def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
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[(X86rep_stos i16)]>, REP, OpSize;
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[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize;
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let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
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def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
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[(X86rep_stos i32)]>, REP;
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[(X86rep_stos i32)], IIC_REP_STOS>, REP;
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let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
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def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
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[(X86rep_stos i64)]>, REP;
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[(X86rep_stos i64)], IIC_REP_STOS>, REP;
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//===----------------------------------------------------------------------===//
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@ -571,7 +576,7 @@ let isCodeGenOnly = 1, Defs = [EFLAGS] in
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def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
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"lock\n\t"
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"or{l}\t{$zero, $dst|$dst, $zero}",
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[]>, Requires<[In32BitMode]>, LOCK;
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[], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK;
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let hasSideEffects = 1 in
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def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
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@ -591,72 +596,72 @@ def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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!strconcat("lock\n\t", mnemonic, "{b}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_NONMEM>, LOCK;
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def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, OpSize, LOCK;
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[], IIC_ALU_NONMEM>, OpSize, LOCK;
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def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_NONMEM>, LOCK;
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def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_NONMEM>, LOCK;
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def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
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ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{b}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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[], IIC_ALU_MEM>, LOCK;
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}
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@ -673,29 +678,29 @@ let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
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def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
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"lock\n\t"
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"inc{b}\t$dst", []>, LOCK;
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"inc{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
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"lock\n\t"
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"inc{w}\t$dst", []>, OpSize, LOCK;
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"inc{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
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def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
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"lock\n\t"
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"inc{l}\t$dst", []>, LOCK;
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"inc{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
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"lock\n\t"
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"inc{q}\t$dst", []>, LOCK;
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"inc{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
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"lock\n\t"
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"dec{b}\t$dst", []>, LOCK;
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"dec{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
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"lock\n\t"
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"dec{w}\t$dst", []>, OpSize, LOCK;
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"dec{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
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def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
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"lock\n\t"
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"dec{l}\t$dst", []>, LOCK;
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"dec{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
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"lock\n\t"
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"dec{q}\t$dst", []>, LOCK;
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"dec{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
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}
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// Atomic compare and swap.
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@ -704,42 +709,42 @@ let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
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def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
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"lock\n\t"
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"cmpxchg8b\t$ptr",
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[(X86cas8 addr:$ptr)]>, TB, LOCK;
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[(X86cas8 addr:$ptr)], IIC_CMPX_LOCK_8B>, TB, LOCK;
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let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
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isCodeGenOnly = 1 in
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def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
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"lock\n\t"
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"cmpxchg16b\t$ptr",
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[(X86cas16 addr:$ptr)]>, TB, LOCK,
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[(X86cas16 addr:$ptr)], IIC_CMPX_LOCK_16B>, TB, LOCK,
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Requires<[HasCmpxchg16b]>;
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let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
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def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
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"lock\n\t"
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"cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
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[(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
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[(X86cas addr:$ptr, GR8:$swap, 1)], IIC_CMPX_LOCK_8>, TB, LOCK;
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}
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let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
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def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
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"lock\n\t"
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"cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
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[(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
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[(X86cas addr:$ptr, GR16:$swap, 2)], IIC_CMPX_LOCK>, TB, OpSize, LOCK;
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}
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let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
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def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
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"lock\n\t"
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"cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
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[(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
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[(X86cas addr:$ptr, GR32:$swap, 4)], IIC_CMPX_LOCK>, TB, LOCK;
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}
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let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
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def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
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"lock\n\t"
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"cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}",
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[(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
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[(X86cas addr:$ptr, GR64:$swap, 8)], IIC_CMPX_LOCK>, TB, LOCK;
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}
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// Atomic exchange and add
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@ -747,22 +752,26 @@ let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
|
||||
def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{b}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
|
||||
[(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))],
|
||||
IIC_XADD_LOCK_MEM8>,
|
||||
TB, LOCK;
|
||||
def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{w}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
|
||||
[(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, OpSize, LOCK;
|
||||
def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{l}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
|
||||
[(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
|
||||
"lock\n\t"
|
||||
"xadd{q}\t{$val, $ptr|$ptr, $val}",
|
||||
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
|
||||
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))],
|
||||
IIC_XADD_LOCK_MEM>,
|
||||
TB, LOCK;
|
||||
}
|
||||
|
||||
|
||||
@ -114,6 +114,9 @@ def IIC_MOVZX : InstrItinClass;
|
||||
def IIC_MOVZX_R16_R8 : InstrItinClass;
|
||||
def IIC_MOVZX_R16_M8 : InstrItinClass;
|
||||
|
||||
def IIC_REP_MOVS : InstrItinClass;
|
||||
def IIC_REP_STOS : InstrItinClass;
|
||||
|
||||
// SSE scalar/parallel binary operations
|
||||
def IIC_SSE_ALU_F32S_RR : InstrItinClass;
|
||||
def IIC_SSE_ALU_F32S_RM : InstrItinClass;
|
||||
@ -250,6 +253,14 @@ def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
|
||||
def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
|
||||
def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
|
||||
|
||||
def IIC_CMPX_LOCK : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_8 : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_8B : InstrItinClass;
|
||||
def IIC_CMPX_LOCK_16B : InstrItinClass;
|
||||
|
||||
def IIC_XADD_LOCK_MEM : InstrItinClass;
|
||||
def IIC_XADD_LOCK_MEM8 : InstrItinClass;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor instruction itineraries.
|
||||
|
||||
@ -144,6 +144,9 @@ def AtomItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
|
||||
|
||||
// SSE binary operations
|
||||
// arithmetic fp scalar
|
||||
InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
|
||||
@ -289,6 +292,14 @@ def AtomItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >
|
||||
]>;
|
||||
InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >
|
||||
]>;
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=x86 < %s | FileCheck %s
|
||||
; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
|
||||
|
||||
define i64 @test1(i32 %xx, i32 %test) nounwind {
|
||||
%conv = zext i32 %xx to i64
|
||||
|
||||
Loading…
Reference in New Issue
Block a user