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Fix a register-class comparison bug in PPCCTRLoops

Browse Source 
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-21 23:23:34 +00:00
parent bb4e619cd9
commit 3ea1b064a0
4 changed files with 3 additions and 20 deletions
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2
lib/Target/PowerPC/PPCCTRLoops.cpp
View File

@ -685,7 +685,7 @@ bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) {
const TargetRegisterClass *SrcRC =
MF->getRegInfo().getRegClass(TripCount->getReg());
CountReg = MF->getRegInfo().createVirtualRegister(RC);
unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ?
unsigned CopyOp = (isPPC64 && GPRC->hasSubClassEq(SrcRC)) ?
(unsigned) PPC::EXTSW_32_64 :
(unsigned) TargetOpcode::COPY;
BuildMI(*Preheader, InsertPos, dl,

9
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -366,15 +366,6 @@ def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
"xor $rA, $rS, $rB", IntSimple,
[(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
// Moves between 32-bit and 64-bit registers (used for copy resolution
// after register allocation).
let isCodeGenOnly = 1 in {
def OR8_32 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
"or $rA, $rS, $rB", IntSimple, []>;
def OR_64 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
"or $rA, $rS, $rB", IntSimple, []>;
}
// Logical ops with immediate.
def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
"andi. $dst, $src1, $src2", IntGeneral,

9
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -422,15 +422,6 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = PPC::VOR;
else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::CROR;
// Asymmetric copies:
else if (PPC::GPRCRegClass.contains(DestReg) &&
PPC::G8RCRegClass.contains(SrcReg))
Opc = PPC::OR_64;
else if (PPC::G8RCRegClass.contains(DestReg) &&
PPC::GPRCRegClass.contains(SrcReg))
Opc = PPC::OR8_32;
else
llvm_unreachable("Impossible reg-to-reg copy");

3
test/CodeGen/PowerPC/asym-regclass-copy.ll
View File

@ -2,7 +2,8 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; This test triggers the use of the asymmetric OR8_32 copy pattern.
; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
; GPRC is handled correctly. When it was not, this test would assert.
@gen_random.last = external unnamed_addr global i64, align 8
@.str = external unnamed_addr constant [4 x i8], align 1