6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 21:32:39 +00:00
Code Issues Projects Releases Wiki Activity

Match a few more obvious patterns to revsh. rdar://9147637.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-03-18 21:52:42 +00:00
parent 1744e476ec
commit 3f30af3f45
3 changed files with 44 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2976,10 +2976,18 @@ def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "revsh", "\t$Rd, $Rm",
[(set GPR:$Rd,
(sext_inreg
(or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
(or (srl GPR:$Rm, (i32 8)),
(shl GPR:$Rm, (i32 8))), i16))]>,
Requires<[IsARM, HasV6]>;
def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
(shl GPR:$Rm, (i32 8))), i16),
(REVSH GPR:$Rm)>;
// Need the AddedComplexity or else MOVs + REV would be chosen.
let AddedComplexity = 5 in
def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
def lsl_shift_imm : SDNodeXForm<imm, [{
unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
return CurDAG->getTargetConstant(Sh, MVT::i32);

8
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -2579,9 +2579,15 @@ def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
"revsh", ".w\t$Rd, $Rm",
[(set rGPR:$Rd,
(sext_inreg
(or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
(or (srl rGPR:$Rm, (i32 8)),
(shl rGPR:$Rm, (i32 8))), i16))]>;
def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
(shl rGPR:$Rm, (i32 8))), i16),
(t2REVSH rGPR:$Rm)>;
def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
def t2PKHBT : T2ThreeReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",

30
test/CodeGen/ARM/rev.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s
define i32 @test1(i32 %X) {
define i32 @test1(i32 %X) nounwind {
; CHECK: test1
; CHECK: rev16 r0, r0
%tmp1 = lshr i32 %X, 8
@ -16,7 +16,7 @@ define i32 @test1(i32 %X) {
ret i32 %tmp14
}
define i32 @test2(i32 %X) {
define i32 @test2(i32 %X) nounwind {
; CHECK: test2
; CHECK: revsh r0, r0
%tmp1 = lshr i32 %X, 8
@ -28,3 +28,29 @@ define i32 @test2(i32 %X) {
%tmp5.upgrd.2 = sext i16 %tmp5 to i32
ret i32 %tmp5.upgrd.2
}
; rdar://9147637
define i32 @test3(i16 zeroext %a) nounwind {
entry:
; CHECK: test3:
; CHECK: revsh r0, r0
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
%1 = sext i16 %0 to i32
ret i32 %1
}
declare i16 @llvm.bswap.i16(i16) nounwind readnone
define i32 @test4(i16 zeroext %a) nounwind {
entry:
; CHECK: test4:
; CHECK: revsh r0, r0
%conv = zext i16 %a to i32
%shr9 = lshr i16 %a, 8
%conv2 = zext i16 %shr9 to i32
%shl = shl nuw nsw i32 %conv, 8
%or = or i32 %conv2, %shl
%sext = shl i32 %or, 16
%conv8 = ashr exact i32 %sext, 16
ret i32 %conv8
}