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Separate decoding for STREXD and LDREXD to make each work better.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-12 17:58:32 +00:00
parent 7a8729effc
commit 3f3570a38b
2 changed files with 24 additions and 7 deletions
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27
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -135,9 +135,10 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
@ -2486,15 +2487,31 @@ static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
return true;
}
static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
return true;
}
static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
if (Inst.getOpcode() == ARM::STREXD)
if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;