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R600: Add support for 24-bit MUL instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
eb643b9b37
commit
3f5d63b956
@ -58,6 +58,9 @@ private:
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bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
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bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
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SDValue SimplifyI24(SDValue &Op);
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bool SelectI24(SDValue Addr, SDValue &Op);
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bool SelectU24(SDValue Addr, SDValue &Op);
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static bool checkType(const Value *ptr, unsigned int addrspace);
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@ -674,7 +677,9 @@ const char *AMDGPUDAGToDAGISel::getPassName() const {
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#endif
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#undef DEBUGTMP
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///==== AMDGPU Functions ====///
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//===----------------------------------------------------------------------===//
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// Complex Patterns
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//===----------------------------------------------------------------------===//
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bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
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SDValue& IntPtr) {
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@ -741,6 +746,49 @@ bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
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return true;
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}
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SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
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APInt Demanded = APInt(32, 0x00FFFFFF);
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APInt KnownZero, KnownOne;
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TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
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const TargetLowering *TLI = getTargetLowering();
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if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
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CurDAG->ReplaceAllUsesWith(Op, TLO.New);
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CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
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return SimplifyI24(TLO.New);
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} else {
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return Op;
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}
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}
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bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
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assert(Op.getValueType() == MVT::i32);
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if (CurDAG->ComputeNumSignBits(Op) == 9) {
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I24 = SimplifyI24(Op);
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return true;
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}
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
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APInt KnownZero;
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APInt KnownOne;
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CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
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assert (Op.getValueType() == MVT::i32);
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// ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
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// i32. These smaller types are legal to use with the i24 instructions.
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if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
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Op.getOpcode() == ISD::ANY_EXTEND ||
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ISD::isEXTLoad(Op.getNode())) {
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U24 = SimplifyI24(Op);
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return true;
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}
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return false;
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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if (Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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@ -173,6 +173,9 @@ def FP_ONE : PatLeaf <
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[{return N->isExactlyValue(1.0);}]
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>;
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def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
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def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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let usesCustomInserter = 1 in {
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@ -366,6 +369,16 @@ class ROTRPattern <Instruction BIT_ALIGN> : Pat <
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(BIT_ALIGN $src0, $src0, $src1)
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>;
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// 24-bit arithmetic patterns
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def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
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/*
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class UMUL24Pattern <Instruction UMUL24> : Pat <
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(mul U24:$x, U24:$y),
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(UMUL24 $x, $y)
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>;
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*/
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include "R600Instructions.td"
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include "SIInstrInfo.td"
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@ -1473,6 +1473,9 @@ let Predicates = [isEGorCayman] in {
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def CNDGE_eg : CNDGE_Common<0x1B>;
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def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
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def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
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def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
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[(set i32:$dst, (mul U24:$src0, U24:$src1))], VecALU
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>;
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def DOT4_eg : DOT4_Common<0xBE>;
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defm CUBE_eg : CUBE_Common<0xC0>;
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@ -1703,6 +1706,10 @@ defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
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let Predicates = [isCayman] in {
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def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
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[(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU
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>;
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let isVector = 1 in {
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def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
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@ -866,14 +866,16 @@ defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
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[(set f32:$dst, (fmul f32:$src0, f32:$src1))]
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>;
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} // End isCommutable = 1
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//defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>;
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defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
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[(set i32:$dst, (mul I24:$src0, I24:$src1))]
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>;
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//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
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//defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>;
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defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
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[(set i32:$dst, (mul U24:$src0, U24:$src1))]
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>;
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//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
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let isCommutable = 1 in {
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defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
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[(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
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19
test/CodeGen/R600/mul_int24.ll
Normal file
19
test/CodeGen/R600/mul_int24.ll
Normal file
@ -0,0 +1,19 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; EG-CHECK: @i32_mul24
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; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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; EG-CHECK: MULLO_INT
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; CM-CHECK: MUL_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI-CHECK: V_MUL_I32_I24
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define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = ashr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = ashr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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65
test/CodeGen/R600/mul_uint24.ll
Normal file
65
test/CodeGen/R600/mul_uint24.ll
Normal file
@ -0,0 +1,65 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; EG-CHECK: @u32_mul24
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; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI-CHECK: @u32_mul24
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; SI-CHECK: V_MUL_U32_U24
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define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = lshr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = lshr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; EG-CHECK: @i16_mul24
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; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
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; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
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; The order of A and B does not matter.
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; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
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; EG-CHECK: 16
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: 16
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; SI-CHECK: @i16_mul24
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; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 16, [[MUL]]
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; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 16, [[LSHL]]
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define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) {
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entry:
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%0 = mul i16 %a, %b
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%1 = sext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; EG-CHECK: @i8_mul24
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; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
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; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
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; The order of A and B does not matter.
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; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
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; The result must be sign-extended
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; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
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; EG-CHECK: 24
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; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
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; EG-CHECK: 24
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; SI-CHECK: @i8_mul24
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; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
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; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 24, [[MUL]]
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; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 24, [[LSHL]]
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define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) {
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entry:
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%0 = mul i8 %a, %b
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%1 = sext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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