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[PowerPC] Correct P7 dispatch unit allocation for vector instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205222 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-03-31 17:02:10 +00:00
parent 5ca1ddf668
commit 3f784d82ff
1 changed files with 8 additions and 16 deletions
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24
lib/Target/PowerPC/PPCScheduleP7.td
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@ -339,36 +339,28 @@ def P7Itineraries : ProcessorItineraries<
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>], InstrStage<1, [P7_VS1, P7_VS2]>],
[5, 1, 1]>, [5, 1, 1]>,
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>], InstrStage<1, [P7_VS1]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>], InstrStage<1, [P7_VS1]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>], InstrStage<1, [P7_VS1]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>], InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>], InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1, P7_VS2]>], InstrStage<1, [P7_VS1, P7_VS2]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS1]>], InstrStage<1, [P7_VS1]>],
[7, 1, 1]>, [7, 1, 1]>,
InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_VS2]>], InstrStage<1, [P7_VS2]>],
[3, 1, 1]> [3, 1, 1]>
]>; ]>;