6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-11 08:29:25 +00:00
Code Issues Projects Releases Wiki Activity

Rename operands to match ARM documentation. No functionality change.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2010-11-30 23:54:45 +00:00
parent b0708d292b
commit 3f8c110dc6
2 changed files with 105 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/ARMInstrFormats.td
View File

@@ -839,7 +839,7 @@ class T1sI<dag oops, dag iops, InstrItinClass itin,
class T1sIt<dag oops, dag iops, InstrItinClass itin, class T1sIt<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
"$lhs = $dst", pattern>; "$Rn = $Rdn", pattern>;
// Thumb1 instruction that can be predicated. // Thumb1 instruction that can be predicated.
class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
@@ -902,7 +902,7 @@ class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
// Helper classes to encode Thumb1 loads and stores. For immediates, the // Helper classes to encode Thumb1 loads and stores. For immediates, the
// following bits are used for "opA": // following bits are used for "opA" (see A6.2.4):
// //
// 0b0110 => Immediate, 4 bytes // 0b0110 => Immediate, 4 bytes
// 0b1000 => Immediate, 2 bytes // 0b1000 => Immediate, 2 bytes

202
lib/Target/ARM/ARMInstrThumb.td
View File

@@ -579,10 +579,15 @@ def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
// Load tconstpool // Load tconstpool
// FIXME: Use ldr.n to work around a Darwin assembler bug. // FIXME: Use ldr.n to work around a Darwin assembler bug.
let canFoldAsLoad = 1, isReMaterializable = 1 in let canFoldAsLoad = 1, isReMaterializable = 1 in
def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i, def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
"ldr", ".n\t$dst, $addr", "ldr", ".n\t$Rt, $addr",
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>, [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59 T1Encoding<{0,1,0,0,1,?}> {
// A6.2 & A8.6.59
bits<3> Rt;
let Inst{10-8} = Rt;
// FIXME: Finish for the addr.
}
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
@@ -632,13 +637,12 @@ def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
[(store tGPR:$src, t_addrmode_sp:$addr)]>, [(store tGPR:$src, t_addrmode_sp:$addr)]>,
T1LdStSP<{0,?,?}>; T1LdStSP<{0,?,?}>;
let mayStore = 1, neverHasSideEffects = 1 in { let mayStore = 1, neverHasSideEffects = 1 in
// Special instruction for spill. It cannot clobber condition register // Special instruction for spill. It cannot clobber condition register when it's
// when it's expanded by eliminateCallFramePseudoInstr(). // expanded by eliminateCallFramePseudoInstr().
def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i, def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
"str", "\t$src, $addr", []>, "str", "\t$src, $addr", []>,
T1LdStSP<{0,?,?}>; T1LdStSP<{0,?,?}>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load / store multiple Instructions. // Load / store multiple Instructions.
@@ -706,15 +710,15 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
// Add with carry register // Add with carry register
let isCommutable = 1, Uses = [CPSR] in let isCommutable = 1, Uses = [CPSR] in
def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, def tADC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
"adc", "\t$dst, $rhs", "adc", "\t$Rdn, $Rm",
[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0101> { T1DataProcessing<0b0101> {
// A8.6.2 // A8.6.2
bits<3> lhs; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = lhs; let Inst{5-3} = Rdn;
let Inst{2-0} = rhs; let Inst{2-0} = Rm;
} }
// Add immediate // Add immediate
@@ -731,15 +735,15 @@ def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
let Inst{2-0} = Rd; let Inst{2-0} = Rd;
} }
def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, def tADDi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
"add", "\t$dst, $rhs", "add", "\t$Rdn, $imm8",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>, [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
T1General<{1,1,0,?,?}> { T1General<{1,1,0,?,?}> {
// A8.6.4 T2 // A8.6.4 T2
bits<3> lhs; bits<3> Rdn;
bits<8> rhs; bits<8> imm8;
let Inst{10-8} = lhs; let Inst{10-8} = Rdn;
let Inst{7-0} = rhs; let Inst{7-0} = imm8;
} }
// Add register // Add register
@@ -771,15 +775,15 @@ def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
// AND register // AND register
let isCommutable = 1 in let isCommutable = 1 in
def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, def tAND : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
"and", "\t$dst, $rhs", "and", "\t$Rdn, $Rm",
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0000> { T1DataProcessing<0b0000> {
// A8.6.12 // A8.6.12
bits<3> rhs; bits<3> Rdn;
bits<3> dst; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// ASR immediate // ASR immediate
@@ -797,27 +801,27 @@ def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
} }
// ASR register // ASR register
def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, def tASRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
"asr", "\t$dst, $rhs", "asr", "\t$Rdn, $Rm",
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0100> { T1DataProcessing<0b0100> {
// A8.6.15 // A8.6.15
bits<3> rhs; bits<3> Rdn;
bits<3> dst; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// BIC register // BIC register
def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, def tBIC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
"bic", "\t$dst, $rhs", "bic", "\t$Rdn, $Rm",
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>, [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
T1DataProcessing<0b1110> { T1DataProcessing<0b1110> {
// A8.6.20 // A8.6.20
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// CMN register // CMN register
@@ -911,15 +915,15 @@ def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
// XOR register // XOR register
let isCommutable = 1 in let isCommutable = 1 in
def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, def tEOR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
"eor", "\t$dst, $rhs", "eor", "\t$Rdn, $Rm",
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0001> { T1DataProcessing<0b0001> {
// A8.6.45 // A8.6.45
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// LSL immediate // LSL immediate
@@ -937,15 +941,15 @@ def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
} }
// LSL register // LSL register
def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, def tLSLrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
"lsl", "\t$dst, $rhs", "lsl", "\t$Rdn, $Rm",
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0010> { T1DataProcessing<0b0010> {
// A8.6.89 // A8.6.89
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// LSR immediate // LSR immediate
@@ -963,15 +967,15 @@ def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
} }
// LSR register // LSR register
def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, def tLSRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
"lsr", "\t$dst, $rhs", "lsr", "\t$Rdn, $Rm",
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0011> { T1DataProcessing<0b0011> {
// A8.6.91 // A8.6.91
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// Move register // Move register
@@ -1014,15 +1018,15 @@ def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
// multiply register // multiply register
let isCommutable = 1 in let isCommutable = 1 in
def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32, def tMUL : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMUL32,
"mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */ "mul", "\t$Rdn, $Rm, $Rdn", /* A8.6.105 MUL Encoding T1 */
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b1101> { T1DataProcessing<0b1101> {
// A8.6.105 // A8.6.105
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// move inverse register // move inverse register
@@ -1039,15 +1043,15 @@ def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
// Bitwise or register // Bitwise or register
let isCommutable = 1 in let isCommutable = 1 in
def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr, def tORR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
"orr", "\t$dst, $rhs", "orr", "\t$Rdn, $Rm",
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b1100> { T1DataProcessing<0b1100> {
// A8.6.114 // A8.6.114
bits<3> dst; bits<3> Rdn;
bits<3> rhs; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// Swaps // Swaps
@@ -1095,15 +1099,15 @@ def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
} }
// rotate right register // rotate right register
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, def tROR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
"ror", "\t$dst, $rhs", "ror", "\t$Rdn, $Rm",
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0111> { T1DataProcessing<0b0111> {
// A8.6.139 // A8.6.139
bits<3> rhs; bits<3> Rdn;
bits<3> dst; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// negate register // negate register
@@ -1120,15 +1124,15 @@ def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
// Subtract with carry register // Subtract with carry register
let Uses = [CPSR] in let Uses = [CPSR] in
def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, def tSBC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
"sbc", "\t$dst, $rhs", "sbc", "\t$Rdn, $Rm",
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>, [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
T1DataProcessing<0b0110> { T1DataProcessing<0b0110> {
// A8.6.151 // A8.6.151
bits<3> rhs; bits<3> Rdn;
bits<3> dst; bits<3> Rm;
let Inst{5-3} = rhs; let Inst{5-3} = Rm;
let Inst{2-0} = dst; let Inst{2-0} = Rdn;
} }
// Subtract immediate // Subtract immediate
@@ -1145,15 +1149,15 @@ def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
let Inst{2-0} = Rd; let Inst{2-0} = Rd;
} }
def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, def tSUBi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
"sub", "\t$dst, $rhs", "sub", "\t$Rdn, $imm8",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>, [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
T1General<{1,1,1,?,?}> { T1General<{1,1,1,?,?}> {
// A8.6.210 T2 // A8.6.210 T2
bits<8> rhs; bits<3> Rdn;
bits<3> dst; bits<8> imm8;
let Inst{10-8} = dst; let Inst{10-8} = Rdn;
let Inst{7-0} = rhs; let Inst{7-0} = imm8;
} }
// subtract register // subtract register