6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-05 01:31:05 +00:00
Code Issues Projects Releases Wiki Activity

Fix a bug in DAGcombiner about zero-extend after setcc.

Browse Source 
For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2013-12-30 02:05:13 +00:00
parent 3796015b5b
commit 3f8f3c9feb
2 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4970,7 +4970,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
}
if (N0.getOpcode() == ISD::SETCC) {
if (!LegalOperations && VT.isVector()) {
if (!LegalOperations && VT.isVector() &&
N0.getValueType().getVectorElementType() == MVT::i1) {
// zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
// Only do this before legalize for now.
EVT N0VT = N0.getOperand(0).getValueType();

10
test/CodeGen/AArch64/neon-shift-left-long.ll
View File

@ -191,3 +191,13 @@ define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {
%tmp = zext <2 x i32> %1 to <2 x i64>
ret <2 x i64> %tmp
}
define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
; CHECK: test_ushll_cmp:
; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
%cmp.i = icmp eq <8 x i8> %a, %b
%vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
%vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>
ret <8 x i16> %vmovl.i.i.i
}