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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-03 15:36:21 +00:00
Fix -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -272,8 +272,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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// perform its own adjustments.
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const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, (SDep &)dep);
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ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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@ -285,8 +285,8 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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continue;
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const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
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if (!UnitLatencies) {
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ComputeOperandLatency(SU, UseSU, (SDep &)dep);
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ST.adjustSchedDependency(SU, UseSU, (SDep &)dep);
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ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
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}
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UseSU->addPred(dep);
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}
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@ -353,8 +353,8 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
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const SDep& dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
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OpSU->Latency, PhysReg);
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if (!isChain && !UnitLatencies) {
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ComputeOperandLatency(OpSU, SU, (SDep &)dep);
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ST.adjustSchedDependency(OpSU, SU, (SDep &)dep);
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ComputeOperandLatency(OpSU, SU, const_cast<SDep &>(dep));
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ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
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}
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SU->addPred(dep);
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@ -80,7 +80,7 @@ std::string JITDebugRegisterer::MakeELF(const Function *F, DebugInfo &I) {
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// Copy the binary into the .text section. This isn't necessary, but it's
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// useful to be able to disassemble the ELF by hand.
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ELFSection &Text = EW.getTextSection((Function *)F);
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ELFSection &Text = EW.getTextSection(const_cast<Function *>(F));
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Text.Addr = (uint64_t)I.FnStart;
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// TODO: We could eliminate this copy if we somehow used a pointer/size pair
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// instead of a vector.
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@ -64,7 +64,8 @@ namespace {
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static char ID;
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public:
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ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(&ID), JTI(0), II((ARMInstrInfo*)tm.getInstrInfo()),
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: MachineFunctionPass(&ID), JTI(0),
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II((const ARMInstrInfo *)tm.getInstrInfo()),
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TD(tm.getTargetData()), TM(tm),
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MCE(mce), MCPEs(0), MJTEs(0),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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@ -174,9 +175,9 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
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II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
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TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
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JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
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II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
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TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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MCPEs = &MF.getConstantPool()->getConstants();
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MJTEs = 0;
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