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Consistently use AnalysisID types in TargetPassConfig.

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This makes it possible to just use a zero value to represent "no pass", so
the phony NoPassID global variable is no longer needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2012-07-02 19:48:37 +00:00
parent 564fbf6aff
commit 3fb99a7368
5 changed files with 71 additions and 75 deletions
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2
include/llvm/CodeGen/MachineScheduler.h
View File

@ -19,7 +19,7 @@
// createCustomMachineSched);
//
// Inside <Target>PassConfig:
// enablePass(MachineSchedulerID);
// enablePass(&MachineSchedulerID);
// MachineSchedRegistry::setDefault(createCustomMachineSched);
//
//===----------------------------------------------------------------------===//

18
include/llvm/CodeGen/Passes.h
View File

@ -32,8 +32,6 @@ namespace llvm {
namespace llvm {
extern char &NoPassID; // Allow targets to choose not to run a pass.
class PassConfigImpl;
/// Target-Independent Code Generator Pass Configuration Options.
@ -101,19 +99,19 @@ public:
/// Allow the target to override a specific pass without overriding the pass
/// pipeline. When passes are added to the standard pipeline at the
/// point where StadardID is expected, add TargetID in its place.
void substitutePass(char &StandardID, char &TargetID);
/// point where StandardID is expected, add TargetID in its place.
void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
/// Insert InsertedPassID pass after TargetPassID pass.
void insertPass(const char &TargetPassID, const char &InsertedPassID);
void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
/// Allow the target to enable a specific standard pass by default.
void enablePass(char &ID) { substitutePass(ID, ID); }
void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
/// Allow the target to disable a specific standard pass by default.
void disablePass(char &ID) { substitutePass(ID, NoPassID); }
void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
/// Return the pass ssubtituted for StandardID by the target.
/// Return the pass substituted for StandardID by the target.
/// If no substitution exists, return StandardID.
AnalysisID getPassSubstitution(AnalysisID StandardID) const;
@ -237,8 +235,8 @@ protected:
///
/// Add a CodeGen pass at this point in the pipeline after checking overrides.
/// Return the pass that was added, or NoPassID.
AnalysisID addPass(char &ID);
/// Return the pass that was added, or zero if no pass was added.
AnalysisID addPass(AnalysisID PassID);
/// Add a pass to the PassManager.
void addPass(Pass *P);

120
lib/CodeGen/Passes.cpp
View File

@ -90,10 +90,10 @@ PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
/// simple binary flags that either suppress the pass or do nothing.
/// i.e. -disable-mypass=false has no effect.
/// These should be converted to boolOrDefault in order to use applyOverride.
static AnalysisID applyDisable(AnalysisID ID, bool Override) {
static AnalysisID applyDisable(AnalysisID PassID, bool Override) {
if (Override)
return &NoPassID;
return ID;
return 0;
return PassID;
}
/// Allow Pass selection to be overriden by command line options. This supports
@ -106,13 +106,13 @@ static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
case cl::BOU_UNSET:
return TargetID;
case cl::BOU_TRUE:
if (TargetID != &NoPassID)
if (TargetID)
return TargetID;
if (StandardID == &NoPassID)
if (StandardID == 0)
report_fatal_error("Target cannot enable pass");
return StandardID;
case cl::BOU_FALSE:
return &NoPassID;
return 0;
}
llvm_unreachable("Invalid command line option state");
}
@ -183,9 +183,6 @@ INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
"Target Pass Configuration", false, false)
char TargetPassConfig::ID = 0;
static char NoPassIDAnchor = 0;
char &llvm::NoPassID = NoPassIDAnchor;
// Pseudo Pass IDs.
char TargetPassConfig::EarlyTailDuplicateID = 0;
char TargetPassConfig::PostRAMachineLICMID = 0;
@ -198,8 +195,8 @@ public:
// that are part of a standard pass pipeline without overridding the entire
// pipeline. This mechanism allows target options to inherit a standard pass's
// user interface. For example, a target may disable a standard pass by
// default by substituting NoPass, and the user may still enable that standard
// pass with an explicit command line option.
// default by substituting a pass ID of zero, and the user may still enable
// that standard pass with an explicit command line option.
DenseMap<AnalysisID,AnalysisID> TargetPasses;
/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
@ -227,18 +224,18 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
initializeCodeGen(*PassRegistry::getPassRegistry());
// Substitute Pseudo Pass IDs for real ones.
substitutePass(EarlyTailDuplicateID, TailDuplicateID);
substitutePass(PostRAMachineLICMID, MachineLICMID);
substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
substitutePass(&PostRAMachineLICMID, &MachineLICMID);
// Temporarily disable experimental passes.
substitutePass(MachineSchedulerID, NoPassID);
substitutePass(&MachineSchedulerID, 0);
}
/// Insert InsertedPassID pass after TargetPassID.
void TargetPassConfig::insertPass(const char &TargetPassID,
const char &InsertedPassID) {
assert(&TargetPassID != &InsertedPassID && "Insert a pass after itself!");
std::pair<AnalysisID, AnalysisID> P(&TargetPassID, &InsertedPassID);
void TargetPassConfig::insertPass(AnalysisID TargetPassID,
AnalysisID InsertedPassID) {
assert(TargetPassID != InsertedPassID && "Insert a pass after itself!");
std::pair<AnalysisID, AnalysisID> P(TargetPassID, InsertedPassID);
Impl->InsertedPasses.push_back(P);
}
@ -261,8 +258,9 @@ void TargetPassConfig::setOpt(bool &Opt, bool Val) {
Opt = Val;
}
void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
Impl->TargetPasses[&StandardID] = &TargetID;
void TargetPassConfig::substitutePass(AnalysisID StandardID,
AnalysisID TargetID) {
Impl->TargetPasses[StandardID] = TargetID;
}
AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
@ -280,12 +278,12 @@ void TargetPassConfig::addPass(Pass *P) {
/// Add a CodeGen pass at this point in the pipeline after checking for target
/// and command line overrides.
AnalysisID TargetPassConfig::addPass(char &ID) {
AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
assert(!Initialized && "PassConfig is immutable");
AnalysisID TargetID = getPassSubstitution(&ID);
AnalysisID FinalID = overridePass(&ID, TargetID);
if (FinalID == &NoPassID)
AnalysisID TargetID = getPassSubstitution(PassID);
AnalysisID FinalID = overridePass(PassID, TargetID);
if (FinalID == 0)
return FinalID;
Pass *P = Pass::createPass(FinalID);
@ -296,7 +294,7 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
I != E; ++I) {
if ((*I).first == &ID) {
if ((*I).first == PassID) {
assert((*I).second && "Illegal Pass ID!");
Pass *NP = Pass::createPass((*I).second);
assert(NP && "Pass ID not registered");
@ -424,11 +422,11 @@ void TargetPassConfig::addMachinePasses() {
assert (TPI && IPI && "Pass ID not registered!");
const char *TID = (char *)(TPI->getTypeInfo());
const char *IID = (char *)(IPI->getTypeInfo());
insertPass(*TID, *IID);
insertPass(TID, IID);
}
// Expand pseudo-instructions emitted by ISel.
addPass(ExpandISelPseudosID);
addPass(&ExpandISelPseudosID);
// Add passes that optimize machine instructions in SSA form.
if (getOptLevel() != CodeGenOpt::None) {
@ -437,7 +435,7 @@ void TargetPassConfig::addMachinePasses() {
else {
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
addPass(LocalStackSlotAllocationID);
addPass(&LocalStackSlotAllocationID);
}
// Run pre-ra passes.
@ -456,7 +454,7 @@ void TargetPassConfig::addMachinePasses() {
printAndVerify("After PostRegAlloc passes");
// Insert prolog/epilog code. Eliminate abstract frame index references...
addPass(PrologEpilogCodeInserterID);
addPass(&PrologEpilogCodeInserterID);
printAndVerify("After PrologEpilogCodeInserter");
/// Add passes that optimize machine instructions after register allocation.
@ -464,7 +462,7 @@ void TargetPassConfig::addMachinePasses() {
addMachineLateOptimization();
// Expand pseudo instructions before second scheduling pass.
addPass(ExpandPostRAPseudosID);
addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
@ -473,12 +471,12 @@ void TargetPassConfig::addMachinePasses() {
// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
addPass(PostRASchedulerID);
addPass(&PostRASchedulerID);
printAndVerify("After PostRAScheduler");
}
// GC
addPass(GCMachineCodeAnalysisID);
addPass(&GCMachineCodeAnalysisID);
if (PrintGCInfo)
addPass(createGCInfoPrinter(dbgs()));
@ -493,30 +491,30 @@ void TargetPassConfig::addMachinePasses() {
/// Add passes that optimize machine instructions in SSA form.
void TargetPassConfig::addMachineSSAOptimization() {
// Pre-ra tail duplication.
if (addPass(EarlyTailDuplicateID) != &NoPassID)
if (addPass(&EarlyTailDuplicateID))
printAndVerify("After Pre-RegAlloc TailDuplicate");
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
addPass(OptimizePHIsID);
addPass(&OptimizePHIsID);
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
addPass(LocalStackSlotAllocationID);
addPass(&LocalStackSlotAllocationID);
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
addPass(DeadMachineInstructionElimID);
addPass(&DeadMachineInstructionElimID);
printAndVerify("After codegen DCE pass");
addPass(MachineLICMID);
addPass(MachineCSEID);
addPass(MachineSinkingID);
addPass(&MachineLICMID);
addPass(&MachineCSEID);
addPass(&MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
addPass(PeepholeOptimizerID);
addPass(&PeepholeOptimizerID);
printAndVerify("After codegen peephole optimization pass");
}
@ -594,8 +592,8 @@ FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
/// Add the minimum set of target-independent passes that are required for
/// register allocation. No coalescing or scheduling.
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(PHIEliminationID);
addPass(TwoAddressInstructionPassID);
addPass(&PHIEliminationID);
addPass(&TwoAddressInstructionPassID);
addPass(RegAllocPass);
printAndVerify("After Register Allocation");
@ -605,7 +603,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
addPass(ProcessImplicitDefsID);
addPass(&ProcessImplicitDefsID);
// LiveVariables currently requires pure SSA form.
//
@ -613,25 +611,25 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// LiveVariables can be removed completely, and LiveIntervals can be directly
// computed. (We still either need to regenerate kill flags after regalloc, or
// preferably fix the scavenger to not depend on them).
addPass(LiveVariablesID);
addPass(&LiveVariablesID);
// Add passes that move from transformed SSA into conventional SSA. This is a
// "copy coalescing" problem.
//
if (!EnableStrongPHIElim) {
// Edge splitting is smarter with machine loop info.
addPass(MachineLoopInfoID);
addPass(PHIEliminationID);
addPass(&MachineLoopInfoID);
addPass(&PHIEliminationID);
}
addPass(TwoAddressInstructionPassID);
addPass(&TwoAddressInstructionPassID);
if (EnableStrongPHIElim)
addPass(StrongPHIEliminationID);
addPass(&StrongPHIEliminationID);
addPass(RegisterCoalescerID);
addPass(&RegisterCoalescerID);
// PreRA instruction scheduling.
if (addPass(MachineSchedulerID) != &NoPassID)
if (addPass(&MachineSchedulerID))
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
@ -643,7 +641,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
printAndVerify("After pre-rewrite passes");
// Finally rewrite virtual registers.
addPass(VirtRegRewriterID);
addPass(&VirtRegRewriterID);
printAndVerify("After Virtual Register Rewriter");
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
@ -658,12 +656,12 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
//
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
addPass(StackSlotColoringID);
addPass(&StackSlotColoringID);
// Run post-ra machine LICM to hoist reloads / remats.
//
// FIXME: can this move into MachineLateOptimization?
addPass(PostRAMachineLICMID);
addPass(&PostRAMachineLICMID);
printAndVerify("After StackSlotColoring and postra Machine LICM");
}
@ -675,33 +673,33 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
/// Add passes that optimize machine instructions after register allocation.
void TargetPassConfig::addMachineLateOptimization() {
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (addPass(BranchFolderPassID) != &NoPassID)
if (addPass(&BranchFolderPassID))
printAndVerify("After BranchFolding");
// Tail duplication.
if (addPass(TailDuplicateID) != &NoPassID)
if (addPass(&TailDuplicateID))
printAndVerify("After TailDuplicate");
// Copy propagation.
if (addPass(MachineCopyPropagationID) != &NoPassID)
if (addPass(&MachineCopyPropagationID))
printAndVerify("After copy propagation pass");
}
/// Add standard basic block placement passes.
void TargetPassConfig::addBlockPlacement() {
AnalysisID ID = &NoPassID;
AnalysisID PassID = 0;
if (!DisableBlockPlacement) {
// MachineBlockPlacement is a new pass which subsumes the functionality of
// CodPlacementOpt. The old code placement pass can be restored by
// disabling block placement, but eventually it will be removed.
ID = addPass(MachineBlockPlacementID);
PassID = addPass(&MachineBlockPlacementID);
} else {
ID = addPass(CodePlacementOptID);
PassID = addPass(&CodePlacementOptID);
}
if (ID != &NoPassID) {
if (PassID) {
// Run a separate pass to collect block placement statistics.
if (EnableBlockPlacementStats)
addPass(MachineBlockPlacementStatsID);
addPass(&MachineBlockPlacementStatsID);
printAndVerify("After machine block placement.");
}

4
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -172,7 +172,7 @@ bool ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
addPass(IfConverterID);
addPass(&IfConverterID);
}
if (getARMSubtarget().isThumb2())
addPass(createThumb2ITBlockPass());
@ -186,7 +186,7 @@ bool ARMPassConfig::addPreEmitPass() {
addPass(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
addPass(UnpackMachineBundlesID);
addPass(&UnpackMachineBundlesID);
}
addPass(createARMConstantIslandPass());

2
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -123,7 +123,7 @@ bool HexagonPassConfig::addPostRegAlloc() {
bool HexagonPassConfig::addPreSched2() {
addPass(IfConverterID);
addPass(&IfConverterID);
return true;
}