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[AVX512] Refactor subvector extracts
No functional change. These are now implemented as two levels of multiclasses heavily relying on the new X86VectorVTInfo class. The multiclass at the first level that is called with float or int provides the 128 or 256 bit subvector extracts. The second level provides the register and memory variants and some more Pat<>s. I've compared the td.expanded files before and after. One change is that ExeDomain for 64x4 is SSEPackedDouble now. I think this is correct, i.e. a bugfix. (BTW, this is the change that was blocked on the recent tablegen fix. The class-instance values X86VectorVTInfo inside vextract_for_type weren't properly evaluated.) Part of <rdar://problem/17688758> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet
parent
1973ffefcf
commit
4007b30ede
@ -64,6 +64,13 @@ class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
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// The string to specify embedded broadcast in assembly.
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string BroadcastStr = "{1to" # NumElts # "}";
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SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
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!if (!eq (Size, 256), sub_ymm, ?));
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Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
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!if (!eq (EltTypeName, "f64"), SSEPackedDouble,
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SSEPackedInt));
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}
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def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
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@ -407,106 +414,70 @@ def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
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//===----------------------------------------------------------------------===//
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// AVX-512 VECTOR EXTRACT
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//---
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let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
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// -- 32x4 form --
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def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512;
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def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
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(ins f128mem:$dst, VR512:$src1, i8imm:$src2),
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"vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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// -- 64x4 form --
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def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W;
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let mayStore = 1 in
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def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
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(ins f256mem:$dst, VR512:$src1, i8imm:$src2),
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"vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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multiclass vextract_for_size<int Opcode,
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X86VectorVTInfo From, X86VectorVTInfo To,
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X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
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PatFrag vextract_extract,
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SDNodeXForm EXTRACT_get_vextract_imm> {
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let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
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def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
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"$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512;
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let mayStore = 1 in
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def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
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(ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
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"vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
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"$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
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}
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// Codegen pattern, e.g. v16i32 -> v4i32 for vextracti32x4
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def : Pat<(vextract_extract:$ext (From.VT VR512:$src1), (iPTR imm)),
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(To.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr") VR512:$src1,
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(EXTRACT_get_vextract_imm To.RC:$ext)))>;
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// Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
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// vextracti32x4
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def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
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(AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
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VR512:$src1,
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(EXTRACT_get_vextract_imm To.RC:$ext)))>;
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// A 128/256-bit subvector extract from the first 512-bit vector position is
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// a subregister copy that needs no instruction.
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def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
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(To.VT
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(EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
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// And for the alternative types.
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def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
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(AltTo.VT
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(EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
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}
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let hasSideEffects = 0 in {
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// -- 32x4 form --
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def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512;
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def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
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(ins i128mem:$dst, VR512:$src1, i8imm:$src2),
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"vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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// -- 64x4 form --
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def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W;
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let mayStore = 1 in
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def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
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(ins i256mem:$dst, VR512:$src1, i8imm:$src2),
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"vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
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ValueType EltVT64, int Opcode64> {
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defm NAME # "32x4" : vextract_for_size<Opcode32,
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X86VectorVTInfo<16, EltVT32, VR512>,
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X86VectorVTInfo< 4, EltVT32, VR128X>,
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X86VectorVTInfo< 8, EltVT64, VR512>,
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X86VectorVTInfo< 2, EltVT64, VR128X>,
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vextract128_extract,
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EXTRACT_get_vextract128_imm>;
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defm NAME # "64x4" : vextract_for_size<Opcode64,
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X86VectorVTInfo< 8, EltVT64, VR512>,
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X86VectorVTInfo< 4, EltVT64, VR256X>,
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X86VectorVTInfo<16, EltVT32, VR512>,
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X86VectorVTInfo< 8, EltVT32, VR256>,
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vextract256_extract,
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EXTRACT_get_vextract256_imm>, VEX_W;
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}
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def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
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(v4f32 (VEXTRACTF32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
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(v4i32 (VEXTRACTI32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
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(v2f64 (VEXTRACTF32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
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(v2i64 (VEXTRACTI32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
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(v8f32 (VEXTRACTF64x4rr VR512:$src1,
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(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
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def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
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(v8i32 (VEXTRACTI64x4rr VR512:$src1,
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(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
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def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
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(v4f64 (VEXTRACTF64x4rr VR512:$src1,
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(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
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def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
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(v4i64 (VEXTRACTI64x4rr VR512:$src1,
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(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
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// A 256-bit subvector extract from the first 512-bit vector position
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// is a subregister copy that needs no instruction.
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def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
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(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
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def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
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(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
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def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
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(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
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def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
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(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
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// zmm -> xmm
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def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
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(v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
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def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
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(v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
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def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
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(v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
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def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
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(v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
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defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
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defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
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// A 128-bit subvector insert to the first 512-bit vector position
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// is a subregister copy that needs no instruction.
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