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32-to-64-bit sign extension pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -299,3 +299,5 @@ def : Pat<(i32 (trunc CPU64Regs:$src)),
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// 32-to-64-bit extension
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def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
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def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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@ -293,6 +293,12 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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if (Subtarget.hasMips64()) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO_64, MVT::i64);
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return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
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}
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO, MVT::i32);
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return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
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