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Proper handle loading of effective address of stack slot stuff

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70737 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2009-05-03 13:10:26 +00:00
parent 82e46c2595
commit 40477317f3
3 changed files with 44 additions and 14 deletions
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24
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
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@@ -132,6 +132,7 @@ void MSP430DAGToDAGISel::InstructionSelect() {
SDNode *MSP430DAGToDAGISel::Select(SDValue Op) { SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode(); SDNode *Node = Op.getNode();
DebugLoc dl = Op.getDebugLoc();
// Dump information about the Node being selected // Dump information about the Node being selected
#ifndef NDEBUG #ifndef NDEBUG
@@ -152,15 +153,20 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
return NULL; return NULL;
} }
// Instruction Selection not handled by the auto-generated tablegen selection // Few custom selection stuff.
// should be handled here. switch (Node->getOpcode()) {
// Something like this: default: break;
// unsigned Opcode = Node->getOpcode(); case ISD::FrameIndex: {
// switch (Opcode) { assert(Op.getValueType() == MVT::i16);
// default: break; int FI = cast<FrameIndexSDNode>(Node)->getIndex();
// case ISD::Foo: SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
// return SelectFoo(Node) if (Node->hasOneUse())
// } return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
TFI, CurDAG->getTargetConstant(0, MVT::i16));
return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16,
TFI, CurDAG->getTargetConstant(0, MVT::i16));
}
}
// Select the default instruction // Select the default instruction
SDNode *ResNode = SelectCode(Op); SDNode *ResNode = SelectCode(Op);

3
lib/Target/MSP430/MSP430InstrInfo.td
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@@ -60,7 +60,6 @@ def memdst : Operand<i16> {
let MIOperandInfo = (ops GR16, i16imm); let MIOperandInfo = (ops GR16, i16imm);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MSP430 Complex Pattern Definitions. // MSP430 Complex Pattern Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -614,7 +613,7 @@ def : Pat<(i8 (trunc GR16:$src)),
(EXTRACT_SUBREG GR16:$src, subreg_8bit)>; (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
// GlobalAddress // GlobalAddress
def : Pat<(i16 (MSP430Wrapper tglobaladdr :$dst)), (MOV16ri tglobaladdr :$dst)>; def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)), def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
(ADD16ri GR16:$src1, tglobaladdr:$src2)>; (ADD16ri GR16:$src1, tglobaladdr:$src2)>;

31
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@@ -152,7 +152,9 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned i = 0; unsigned i = 0;
MachineInstr &MI = *II; MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent(); MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
DebugLoc dl = MI.getDebugLoc();
while (!MI.getOperand(i).isFI()) { while (!MI.getOperand(i).isFI()) {
++i; ++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -169,10 +171,33 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Skip the saved PC // Skip the saved PC
Offset += 2; Offset += 2;
MI.getOperand(i).ChangeToRegister(BasePtr, false);
// Fold imm into offset // Fold imm into offset
Offset += MI.getOperand(i+1).getImm(); Offset += MI.getOperand(i+1).getImm();
if (MI.getOpcode() == MSP430::ADD16ri) {
// This is actually "load effective address" of the stack slot
// instruction. We have only two-address instructions, thus we need to
// expand it into mov + add
MI.setDesc(TII.get(MSP430::MOV16rr));
MI.getOperand(i).ChangeToRegister(BasePtr, false);
if (Offset == 0)
return;
// We need to materialize the offset via add instruction.
unsigned DstReg = MI.getOperand(0).getReg();
if (Offset < 0)
BuildMI(MBB, next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
.addReg(DstReg).addImm(-Offset);
else
BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
.addReg(DstReg).addImm(Offset);
return;
}
MI.getOperand(i).ChangeToRegister(BasePtr, false);
MI.getOperand(i+1).ChangeToImmediate(Offset); MI.getOperand(i+1).ChangeToImmediate(Offset);
} }