mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-30 04:35:00 +00:00
Now that we handle all allocas via a non-SP reg offset remove all of the
special case handling for ARM::SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116688 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
4c8a985ed5
commit
404be0c04f
@ -56,11 +56,6 @@ namespace {
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class ARMFastISel : public FastISel {
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typedef struct AddrBase {
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unsigned Reg;
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unsigned FrameIndex;
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} AddrBase;
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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@ -142,10 +137,10 @@ class ARMFastISel : public FastISel {
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private:
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bool isTypeLegal(const Type *Ty, EVT &VT);
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bool isLoadTypeLegal(const Type *Ty, EVT &VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, AddrBase Base, int Offset);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, AddrBase Base, int Offset);
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bool ARMComputeRegOffset(const Value *Obj, AddrBase &Base, int &Offset);
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void ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
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void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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unsigned ARMMaterializeInt(const Constant *C, EVT VT);
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unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
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@ -567,7 +562,7 @@ bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
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}
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// Computes the Reg+Offset to get to an object.
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bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
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bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
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int &Offset) {
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// Some boilerplate from the X86 FastISel.
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const User *U = NULL;
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@ -612,7 +607,7 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
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}
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case Instruction::GetElementPtr: {
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int SavedOffset = Offset;
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AddrBase SavedBase = Base;
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unsigned SavedBase = Base;
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int TmpOffset = Offset;
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// Iterate through the GEP folding the constants into offsets where
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@ -665,7 +660,7 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
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if (Reg == 0) return false;
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Base.Reg = Reg;
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Base = Reg;
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return true;
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}
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}
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@ -676,20 +671,22 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
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unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
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if (Tmp == 0) return false;
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Base.Reg = Tmp;
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Base = Tmp;
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return true;
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}
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// Try to get this in a register if nothing else has worked.
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if (Base.Reg == 0) Base.Reg = getRegForValue(Obj);
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return Base.Reg != 0;
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if (Base == 0) Base = getRegForValue(Obj);
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return Base != 0;
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}
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void ARMFastISel::ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT) {
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void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
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assert (Base != ARM::SP && "How'd we get a stack pointer here?");
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// Since the offset may be too large for the load instruction
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// get the reg+offset into a register.
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if (Base.Reg != ARM::SP && Offset != 0) {
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if (Offset != 0) {
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ARMCC::CondCodes Pred = ARMCC::AL;
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unsigned PredReg = 0;
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@ -699,21 +696,21 @@ void ARMFastISel::ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT) {
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if (!isThumb)
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emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Base.Reg, Offset, Pred, PredReg,
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BaseReg, Base, Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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else {
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assert(AFI->isThumb2Function());
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emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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BaseReg, Base.Reg, Offset, Pred, PredReg,
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BaseReg, Base, Offset, Pred, PredReg,
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static_cast<const ARMBaseInstrInfo&>(TII));
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}
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Offset = 0;
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Base.Reg = BaseReg;
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Base = BaseReg;
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}
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}
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bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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AddrBase Base, int Offset) {
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unsigned Base, int Offset) {
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assert(VT.isSimple() && "Non-simple types are invalid here!");
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unsigned Opc;
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@ -750,44 +747,24 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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}
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ResultReg = createResultReg(RC);
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// All SP loads should already have been lowered to another reg.
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assert(Base != ARM::SP && "No stack stores this late!");
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// For now with the additions above the offset should be zero - thus we
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// can always fit into an i12.
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assert((Base.Reg == ARM::SP || Offset == 0) &&
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"Offset not zero and not a stack load!");
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assert(Offset == 0 && "Offset should be zero at this point!");
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if (Base.Reg == ARM::SP && Offset == 0)
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TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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ResultReg, Base.FrameIndex, RC,
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TM.getRegisterInfo());
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else if (Base.Reg == ARM::SP) {
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// TODO: This won't work for NEON.
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unsigned FI = Base.FrameIndex;
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MachineMemOperand *MMO =
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FuncInfo.MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI, Offset),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
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}
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// The thumb and floating point instructions both take 2 operands, ARM takes
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// another register.
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else if (isFloat || isThumb)
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base.Reg).addImm(Offset));
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.addReg(Base).addImm(Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Base.Reg).addReg(0).addImm(Offset));
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.addReg(Base).addReg(0).addImm(Offset));
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return true;
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}
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@ -798,7 +775,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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return false;
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// Our register and offset with innocuous defaults.
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AddrBase Base = { 0, 0 };
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unsigned Base = 0;
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int Offset = 0;
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// See if we can handle this as Reg + Offset
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@ -815,7 +792,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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}
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bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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AddrBase Base, int Offset) {
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unsigned Base, int Offset) {
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unsigned StrOpc;
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bool isFloat = false;
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// VT is set here only for use in the alloca stores below - those are promoted
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@ -846,40 +823,23 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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break;
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}
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if (Base.Reg == ARM::SP && Offset == 0)
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TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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SrcReg, true /*isKill*/, Base.FrameIndex,
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TLI.getRegClassFor(VT), TM.getRegisterInfo());
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else if (Base.Reg == ARM::SP) {
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// TODO: This won't work for NEON.
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unsigned FI = Base.FrameIndex;
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MachineMemOperand *MMO =
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FuncInfo.MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI, Offset),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg, getKillRegState(true))
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg, getKillRegState(true))
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.addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
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}
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// All SP stores should already have been lowered to another reg.
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assert(Base != ARM::SP && "No stack stores this late!");
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// For now with the additions above the offset should be zero - thus we
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// can always fit into an i12.
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assert(Offset == 0 && "Offset should be zero at this point!");
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// The thumb addressing mode has operands swapped from the arm addressing
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// mode, the floating point one only has two operands.
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else if (isFloat || isThumb)
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Base.Reg).addImm(Offset));
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.addReg(SrcReg).addReg(Base).addImm(Offset));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg).addReg(Base.Reg).addReg(0).addImm(Offset));
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.addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
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return true;
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}
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@ -899,7 +859,7 @@ bool ARMFastISel::SelectStore(const Instruction *I) {
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return false;
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// Our register and offset with innocuous defaults.
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AddrBase Base = { 0, 0 };
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unsigned Base = 0;
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int Offset = 0;
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// See if we can handle this as Reg + Offset
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