mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Use descriptive variable names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
5f16057d1e
commit
4061da1403
@ -733,13 +733,13 @@ MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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unsigned Oldval = MI->getOperand(0).getReg();
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unsigned OldVal = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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unsigned Incr = MI->getOperand(2).getReg();
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unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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unsigned StoreVal = RegInfo.createVirtualRegister(RC);
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unsigned AndRes = RegInfo.createVirtualRegister(RC);
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unsigned Success = RegInfo.createVirtualRegister(RC);
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -765,25 +765,27 @@ MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// loopMBB:
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// ll oldval, 0(ptr)
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// <binop> tmp1, oldval, incr
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// sc tmp3, tmp1, 0(ptr)
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// beq tmp3, $0, loopMBB
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// <binop> storeval, oldval, incr
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// sc success, storeval, 0(ptr)
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// beq success, $0, loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0);
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if (Nand) {
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// and tmp2, oldval, incr
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// nor tmp1, $0, tmp2
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr);
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BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
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// and andres, oldval, incr
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// nor storeval, $0, andres
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BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr);
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BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal)
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.addReg(Mips::ZERO).addReg(AndRes);
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} else if (BinOpcode) {
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// <binop> tmp1, oldval, incr
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BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr);
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// <binop> storeval, oldval, incr
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BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
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} else {
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Tmp1 = Incr;
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StoreVal = Incr;
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}
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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.addReg(StoreVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Tmp3).addReg(Mips::ZERO).addMBB(loopMBB);
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.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
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MI->eraseFromParent(); // The instruction is gone now.
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@ -808,24 +810,24 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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unsigned Ptr = MI->getOperand(1).getReg();
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unsigned Incr = MI->getOperand(2).getReg();
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unsigned Addr = RegInfo.createVirtualRegister(RC);
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unsigned Shift = RegInfo.createVirtualRegister(RC);
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unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
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unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
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unsigned Mask = RegInfo.createVirtualRegister(RC);
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unsigned Mask2 = RegInfo.createVirtualRegister(RC);
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unsigned Newval = RegInfo.createVirtualRegister(RC);
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unsigned Oldval = RegInfo.createVirtualRegister(RC);
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unsigned NewVal = RegInfo.createVirtualRegister(RC);
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unsigned OldVal = RegInfo.createVirtualRegister(RC);
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unsigned Incr2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp10 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp11 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp12 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp13 = RegInfo.createVirtualRegister(RC);
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unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
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unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
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unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
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unsigned AndRes = RegInfo.createVirtualRegister(RC);
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unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
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unsigned MaskOldVal0 = RegInfo.createVirtualRegister(RC);
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unsigned StoreVal = RegInfo.createVirtualRegister(RC);
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unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
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unsigned SrlRes = RegInfo.createVirtualRegister(RC);
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unsigned SllRes = RegInfo.createVirtualRegister(RC);
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unsigned Success = RegInfo.createVirtualRegister(RC);
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -850,84 +852,93 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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sinkMBB->addSuccessor(exitMBB);
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// thisMBB:
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// addiu tmp1,$0,-4 # 0xfffffffc
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// and addr,ptr,tmp1
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// andi tmp2,ptr,3
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// sll shift,tmp2,3
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// ori tmp3,$0,255 # 0xff
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// sll mask,tmp3,shift
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// addiu masklsb2,$0,-4 # 0xfffffffc
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// and alignedaddr,ptr,masklsb2
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// andi ptrlsb2,ptr,3
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// sll shiftamt,ptrlsb2,3
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// ori maskupper,$0,255 # 0xff
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// sll mask,maskupper,shiftamt
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// nor mask2,$0,mask
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// sll incr2,incr,shift
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// sll incr2,incr,shiftamt
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int64_t MaskImm = (Size == 1) ? 255 : 65535;
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BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
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BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
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BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
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BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
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BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
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BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
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BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
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.addReg(Mips::ZERO).addImm(-4);
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BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
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.addReg(Ptr).addReg(MaskLSB2);
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BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
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BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
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BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
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.addReg(Mips::ZERO).addImm(MaskImm);
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BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(MaskUpper).addReg(ShiftAmt);
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BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(Shift);
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BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Incr).addReg(ShiftAmt);
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// atomic.load.binop
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// loopMBB:
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// ll oldval,0(addr)
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// binop tmp7,oldval,incr2
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// and newval,tmp7,mask
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// and tmp8,oldval,mask2
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// or tmp9,tmp8,newval
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// sc tmp13,tmp9,0(addr)
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// beq tmp13,$0,loopMBB
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// ll oldval,0(alignedaddr)
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// binop binopres,oldval,incr2
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// and newval,binopres,mask
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// and maskedoldval0,oldval,mask2
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// or storeval,maskedoldval0,newval
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// sc success,storeval,0(alignedaddr)
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// beq success,$0,loopMBB
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// atomic.swap
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// loopMBB:
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// ll oldval,0(addr)
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// ll oldval,0(alignedaddr)
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// and newval,incr2,mask
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// and tmp8,oldval,mask2
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// or tmp9,tmp8,newval
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// sc tmp13,tmp9,0(addr)
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// beq tmp13,$0,loopMBB
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// and maskedoldval0,oldval,mask2
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// or storeval,maskedoldval0,newval
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// sc success,storeval,0(alignedaddr)
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// beq success,$0,loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
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if (Nand) {
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// and tmp6, oldval, incr2
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// nor tmp7, $0, tmp6
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
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BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
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// and andres, oldval, incr2
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// nor binopres, $0, andres
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// and newval, binopres, mask
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BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
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.addReg(Mips::ZERO).addReg(AndRes);
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BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
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} else if (BinOpcode) {
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// <binop> tmp7, oldval, incr2
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BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
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// <binop> binopres, oldval, incr2
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// and newval, binopres, mask
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BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
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BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
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} else {// atomic.swap
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BuildMI(BB, dl, TII->get(Mips::ANDi), Newval).addReg(Incr2).addReg(Mask);
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// and newval, incr2, mask
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BuildMI(BB, dl, TII->get(Mips::ANDi), NewVal).addReg(Incr2).addReg(Mask);
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}
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2);
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp13)
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.addReg(Tmp9).addReg(Addr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::AND), MaskOldVal0)
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.addReg(OldVal).addReg(Mask2);
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BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
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.addReg(MaskOldVal0).addReg(NewVal);
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB);
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.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
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// sinkMBB:
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// and tmp10,oldval,mask
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// srl tmp11,tmp10,shift
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// sll tmp12,tmp11,24
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// sra dest,tmp12,24
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// and maskedoldval1,oldval,mask
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// srl srlres,maskedoldval1,shiftamt
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// sll sllres,srlres,24
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// sra dest,sllres,24
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BB = sinkMBB;
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int64_t ShiftImm = (Size == 1) ? 24 : 16;
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp10)
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.addReg(Oldval).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::SRL), Tmp11)
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.addReg(Tmp10).addReg(Shift);
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BuildMI(BB, dl, TII->get(Mips::SLL), Tmp12)
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.addReg(Tmp11).addImm(ShiftImm);
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BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
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.addReg(OldVal).addReg(Mask);
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BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes)
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.addReg(MaskedOldVal1).addReg(ShiftAmt);
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BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
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.addReg(SrlRes).addImm(ShiftImm);
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BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
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.addReg(Tmp12).addImm(ShiftImm);
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.addReg(SllRes).addImm(ShiftImm);
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MI->eraseFromParent(); // The instruction is gone now.
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@ -948,10 +959,10 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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unsigned Oldval = MI->getOperand(2).getReg();
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unsigned Newval = MI->getOperand(3).getReg();
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unsigned OldVal = MI->getOperand(2).getReg();
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unsigned NewVal = MI->getOperand(3).getReg();
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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unsigned Success = RegInfo.createVirtualRegister(RC);
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -985,15 +996,16 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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BB = loop1MBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BNE))
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.addReg(Dest).addReg(Oldval).addMBB(exitMBB);
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.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
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// loop2MBB:
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// sc tmp3, tmp1, 0(ptr)
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// beq tmp3, $0, loop1MBB
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// sc success, newval, 0(ptr)
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// beq success, $0, loop1MBB
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BB = loop2MBB;
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::SC), Success)
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.addReg(NewVal).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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.addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB);
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.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
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MI->eraseFromParent(); // The instruction is gone now.
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@ -1015,27 +1027,27 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Ptr = MI->getOperand(1).getReg();
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unsigned Oldval = MI->getOperand(2).getReg();
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unsigned Newval = MI->getOperand(3).getReg();
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unsigned CmpVal = MI->getOperand(2).getReg();
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unsigned NewVal = MI->getOperand(3).getReg();
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unsigned Addr = RegInfo.createVirtualRegister(RC);
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unsigned Shift = RegInfo.createVirtualRegister(RC);
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unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
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unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
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unsigned Mask = RegInfo.createVirtualRegister(RC);
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unsigned Mask2 = RegInfo.createVirtualRegister(RC);
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unsigned Oldval2 = RegInfo.createVirtualRegister(RC);
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unsigned Oldval3 = RegInfo.createVirtualRegister(RC);
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unsigned Oldval4 = RegInfo.createVirtualRegister(RC);
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unsigned Newval2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp1 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp2 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp4 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp5 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp6 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp7 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp8 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp9 = RegInfo.createVirtualRegister(RC);
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unsigned Tmp10 = RegInfo.createVirtualRegister(RC);
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unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
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unsigned OldVal = RegInfo.createVirtualRegister(RC);
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unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
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unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
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unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
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unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
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unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
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unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
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unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
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unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
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unsigned StoreVal = RegInfo.createVirtualRegister(RC);
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unsigned SrlRes = RegInfo.createVirtualRegister(RC);
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unsigned SllRes = RegInfo.createVirtualRegister(RC);
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unsigned Success = RegInfo.createVirtualRegister(RC);
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -1065,66 +1077,77 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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// FIXME: computation of newval2 can be moved to loop2MBB.
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// thisMBB:
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// addiu tmp1,$0,-4 # 0xfffffffc
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// and addr,ptr,tmp1
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// andi tmp2,ptr,3
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// sll shift,tmp2,3
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// ori tmp3,$0,255 # 0xff
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// sll mask,tmp3,shift
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// addiu masklsb2,$0,-4 # 0xfffffffc
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// and alignedaddr,ptr,masklsb2
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// andi ptrlsb2,ptr,3
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// sll shiftamt,ptrlsb2,3
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// ori maskupper,$0,255 # 0xff
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// sll mask,maskupper,shiftamt
|
||||
// nor mask2,$0,mask
|
||||
// andi tmp4,oldval,255
|
||||
// sll oldval2,tmp4,shift
|
||||
// andi tmp5,newval,255
|
||||
// sll newval2,tmp5,shift
|
||||
// andi maskedcmpval,cmpval,255
|
||||
// sll shiftedcmpval,maskedcmpval,shiftamt
|
||||
// andi maskednewval,newval,255
|
||||
// sll shiftednewval,maskednewval,shiftamt
|
||||
int64_t MaskImm = (Size == 1) ? 255 : 65535;
|
||||
BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4);
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3);
|
||||
BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift);
|
||||
BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
|
||||
.addReg(Mips::ZERO).addImm(-4);
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
|
||||
.addReg(Ptr).addReg(MaskLSB2);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
|
||||
BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
|
||||
.addReg(Mips::ZERO).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Mask)
|
||||
.addReg(MaskUpper).addReg(ShiftAmt);
|
||||
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
|
||||
.addReg(CmpVal).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedCmpVal)
|
||||
.addReg(MaskedCmpVal).addReg(ShiftAmt);
|
||||
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
|
||||
.addReg(NewVal).addImm(MaskImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftedNewVal)
|
||||
.addReg(MaskedNewVal).addReg(ShiftAmt);
|
||||
|
||||
// loop1MBB:
|
||||
// ll oldval3,0(addr)
|
||||
// and oldval4,oldval3,mask
|
||||
// bne oldval4,oldval2,sinkMBB
|
||||
// ll oldval,0(alginedaddr)
|
||||
// and maskedoldval0,oldval,mask
|
||||
// bne maskedoldval0,shiftedcmpval,sinkMBB
|
||||
BB = loop1MBB;
|
||||
BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0);
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask);
|
||||
BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
|
||||
.addReg(OldVal).addReg(Mask);
|
||||
BuildMI(BB, dl, TII->get(Mips::BNE))
|
||||
.addReg(Oldval4).addReg(Oldval2).addMBB(sinkMBB);
|
||||
.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
|
||||
|
||||
// loop2MBB:
|
||||
// and tmp6,oldval3,mask2
|
||||
// or tmp7,tmp6,newval2
|
||||
// sc tmp10,tmp7,0(addr)
|
||||
// beq tmp10,$0,loop1MBB
|
||||
// and maskedoldval1,oldval,mask2
|
||||
// or storeval,maskedoldval1,shiftednewval
|
||||
// sc success,storeval,0(alignedaddr)
|
||||
// beq success,$0,loop1MBB
|
||||
BB = loop2MBB;
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2);
|
||||
BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2);
|
||||
BuildMI(BB, dl, TII->get(Mips::SC), Tmp10)
|
||||
.addReg(Tmp7).addReg(Addr).addImm(0);
|
||||
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
|
||||
.addReg(OldVal).addReg(Mask2);
|
||||
BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
|
||||
.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
|
||||
BuildMI(BB, dl, TII->get(Mips::SC), Success)
|
||||
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
|
||||
BuildMI(BB, dl, TII->get(Mips::BEQ))
|
||||
.addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB);
|
||||
.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
|
||||
|
||||
// sinkMBB:
|
||||
// srl tmp8,oldval4,shift
|
||||
// sll tmp9,tmp8,24
|
||||
// sra dest,tmp9,24
|
||||
// srl srlres,maskedoldval0,shiftamt
|
||||
// sll sllres,srlres,24
|
||||
// sra dest,sllres,24
|
||||
BB = sinkMBB;
|
||||
int64_t ShiftImm = (Size == 1) ? 24 : 16;
|
||||
|
||||
BuildMI(BB, dl, TII->get(Mips::SRL), Tmp8)
|
||||
.addReg(Oldval4).addReg(Shift);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), Tmp9)
|
||||
.addReg(Tmp8).addImm(ShiftImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SRL), SrlRes)
|
||||
.addReg(MaskedOldVal0).addReg(ShiftAmt);
|
||||
BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
|
||||
.addReg(SrlRes).addImm(ShiftImm);
|
||||
BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
|
||||
.addReg(Tmp9).addImm(ShiftImm);
|
||||
.addReg(SllRes).addImm(ShiftImm);
|
||||
|
||||
MI->eraseFromParent(); // The instruction is gone now.
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user