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https://github.com/c64scene-ar/llvm-6502.git
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[FastISel][X86] Refactor the code to get the X86 condition from a helper function. NFC.
Make use of helper functions to simplify the branch and compare instruction selection in FastISel. Also add test cases for compare and conditonal branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211077 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
@@ -16,6 +16,7 @@
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#include "X86.h"
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#include "X86CallingConv.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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@@ -154,6 +155,44 @@ private:
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} // end anonymous namespace.
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static std::pair<X86::CondCode, bool>
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getX86ConditonCode(CmpInst::Predicate Predicate) {
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X86::CondCode CC = X86::COND_INVALID;
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bool NeedSwap = false;
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switch (Predicate) {
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default: break;
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// Floating-point Predicates
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case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
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case CmpInst::FCMP_OLT: NeedSwap = true; // fall-through
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case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
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case CmpInst::FCMP_OLE: NeedSwap = true; // fall-through
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case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
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case CmpInst::FCMP_UGT: NeedSwap = true; // fall-through
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case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
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case CmpInst::FCMP_UGE: NeedSwap = true; // fall-through
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case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
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case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
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case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
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case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
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case CmpInst::FCMP_OEQ: // fall-through
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case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
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// Integer Predicates
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case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
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case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
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case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
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case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
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case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
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case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
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case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
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case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
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case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
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case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
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}
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return std::make_pair(CC, NeedSwap);
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}
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bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
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EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
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if (evt == MVT::Other || !evt.isSimple())
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@@ -1009,73 +1048,51 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
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if (!isTypeLegal(I->getOperand(0)->getType(), VT))
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return false;
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unsigned ResultReg = createResultReg(&X86::GR8RegClass);
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unsigned SetCCOpc;
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bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
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// FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
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static unsigned SETFOpcTable[2][2] = {
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{ X86::SETEr, X86::SETNPr },
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{ X86::SETNEr, X86::SETPr }
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};
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unsigned *SETFOpc = nullptr;
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switch (CI->getPredicate()) {
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case CmpInst::FCMP_OEQ: {
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default: break;
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case CmpInst::FCMP_OEQ: SETFOpc = &SETFOpcTable[0][0]; break;
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case CmpInst::FCMP_UNE: SETFOpc = &SETFOpcTable[1][0]; break;
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}
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unsigned ResultReg = createResultReg(&X86::GR8RegClass);
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if (SETFOpc) {
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if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
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return false;
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unsigned EReg = createResultReg(&X86::GR8RegClass);
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unsigned NPReg = createResultReg(&X86::GR8RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETEr), EReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(X86::SETNPr), NPReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
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unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
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unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[0]),
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FlagReg1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[1]),
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FlagReg2);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::AND8rr),
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ResultReg).addReg(FlagReg1).addReg(FlagReg2);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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case CmpInst::FCMP_UNE: {
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if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
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return false;
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unsigned NEReg = createResultReg(&X86::GR8RegClass);
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unsigned PReg = createResultReg(&X86::GR8RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETNEr), NEReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETPr), PReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::OR8rr),ResultReg)
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.addReg(PReg).addReg(NEReg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
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case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
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case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
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case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
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case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
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case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
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case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
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case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
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case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
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case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
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case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
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case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
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X86::CondCode CC;
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bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
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std::tie(CC, SwapArgs) = getX86ConditonCode(CI->getPredicate());
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assert(CC <= X86::LAST_VALID_COND && "Unexpected conditon code.");
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unsigned Opc = X86::getSETFromCond(CC);
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case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
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case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
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case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
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case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
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case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
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case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
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case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
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case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
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case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
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case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
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default:
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return false;
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}
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const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
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const Value *LHS = CI->getOperand(0);
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const Value *RHS = CI->getOperand(1);
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if (SwapArgs)
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std::swap(Op0, Op1);
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std::swap(LHS, RHS);
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// Emit a compare of Op0/Op1.
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if (!X86FastEmitCompare(Op0, Op1, VT))
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if (!X86FastEmitCompare(LHS, RHS, VT))
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return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SetCCOpc), ResultReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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@@ -1152,66 +1169,59 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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Predicate = CmpInst::getInversePredicate(Predicate);
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}
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bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
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unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
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// FCMP_OEQ and FCMP_UNE cannot be expressed with a single flag/conditon
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// code check. Instead two branch instructions are required to check all
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// the flags. First we change the predicate to a supported conditon code,
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// which will be the first branch. Later one we will emit the second
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// branch.
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bool NeedExtraBranch = false;
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switch (Predicate) {
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default: break;
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case CmpInst::FCMP_OEQ:
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std::swap(TrueMBB, FalseMBB);
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Predicate = CmpInst::FCMP_UNE;
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// FALL THROUGH
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case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
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case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
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case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
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case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
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case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
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case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
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case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
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case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
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case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
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case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
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case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
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case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
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case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
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case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
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case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
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case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
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case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
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case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
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case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
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case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
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case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
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default:
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return false;
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std::swap(TrueMBB, FalseMBB); // fall-through
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case CmpInst::FCMP_UNE:
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NeedExtraBranch = true;
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Predicate = CmpInst::FCMP_ONE;
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break;
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}
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const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
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X86::CondCode CC;
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bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
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unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
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std::tie(CC, SwapArgs) = getX86ConditonCode(Predicate);
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assert(CC <= X86::LAST_VALID_COND && "Unexpected conditon code.");
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BranchOpc = X86::GetCondBranchFromCond(CC);
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const Value *CmpLHS = CI->getOperand(0);
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const Value *CmpRHS = CI->getOperand(1);
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if (SwapArgs)
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std::swap(Op0, Op1);
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std::swap(CmpLHS, CmpRHS);
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// Emit a compare of the LHS and RHS, setting the flags.
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if (!X86FastEmitCompare(Op0, Op1, VT))
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if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT))
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return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
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.addMBB(TrueMBB);
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if (Predicate == CmpInst::FCMP_UNE) {
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// X86 requires a second branch to handle UNE (and OEQ,
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// which is mapped to UNE above).
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// X86 requires a second branch to handle UNE (and OEQ, which is mapped
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// to UNE above).
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if (NeedExtraBranch) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_4))
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.addMBB(TrueMBB);
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}
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FastEmitBranch(FalseMBB, DbgLoc);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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TrueMBB->getBasicBlock());
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FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
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// Emits an unconditional branch to the FalseBB, obtains the branch
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// weight, andd adds it to the successor list.
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FastEmitBranch(FalseMBB, DbgLoc);
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return true;
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}
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} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
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