misched: Use the TargetSchedModel interface wherever possible.

Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/MachineScheduler.h

@@ -31,7 +31,6 @@
 #include "llvm/CodeGen/RegisterPressure.h"
 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/MC/MCInstrItineraries.h"
 
 namespace llvm {
 
@@ -278,19 +277,6 @@ public:
     return RegionCriticalPSets;
   }
 
-  /// getIssueWidth - Return the max instructions per scheduling group.
-  unsigned getIssueWidth() const {
-    return (InstrItins && InstrItins->SchedModel)
-      ? InstrItins->SchedModel->IssueWidth : 1;
-  }
-
-  /// getNumMicroOps - Return the number of issue slots required for this MI.
-  unsigned getNumMicroOps(MachineInstr *MI) const {
-    if (!InstrItins) return 1;
-    int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
-    return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
-  }
-
 protected:
   // Top-Level entry points for the schedule() driver...
 

include/llvm/CodeGen/ScheduleDAG.h

@@ -570,11 +570,6 @@ namespace llvm {
     unsigned VerifyScheduledDAG(bool isBottomUp);
 #endif
 
-  protected:
-    /// ComputeLatency - Compute node latency.
-    ///
-    virtual void computeLatency(SUnit *SU) = 0;
-
   private:
     // Return the MCInstrDesc of this SDNode or NULL.
     const MCInstrDesc *getNodeDesc(const SDNode *Node) const;

include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -111,7 +111,6 @@ namespace llvm {
     const MachineLoopInfo &MLI;
     const MachineDominatorTree &MDT;
     const MachineFrameInfo *MFI;
-    const InstrItineraryData *InstrItins;
 
     /// Live Intervals provides reaching defs in preRA scheduling.
     LiveIntervals *LIS;
@@ -187,6 +186,9 @@ namespace llvm {
 
     virtual ~ScheduleDAGInstrs() {}
 
+    /// \brief Get the machine model for instruction scheduling.
+    const TargetSchedModel *getSchedModel() const { return &SchedModel; }
+
     /// begin - Return an iterator to the top of the current scheduling region.
     MachineBasicBlock::iterator begin() const { return RegionBegin; }
 
@@ -227,10 +229,6 @@ namespace llvm {
     /// used by instructions in the fallthrough block.
     void addSchedBarrierDeps();
 
-    /// computeLatency - Compute node latency.
-    ///
-    virtual void computeLatency(SUnit *SU);
-
     /// schedule - Order nodes according to selected style, filling
     /// in the Sequence member.
     ///

include/llvm/CodeGen/TargetSchedule.h

@@ -55,12 +55,29 @@ public:
   /// latency properties, but separate from the per-cycle itinerary data.
   bool hasInstrSchedModel() const;
 
+  const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
+
   /// \brief Return true if this machine model includes cycle-to-cycle itinerary
   /// data.
   ///
   /// This models scheduling at each stage in the processor pipeline.
   bool hasInstrItineraries() const;
 
+  const InstrItineraryData *getInstrItineraries() const {
+    if (hasInstrItineraries())
+      return &InstrItins;
+    return 0;
+  }
+
+  /// \brief Identify the processor corresponding to the current subtarget.
+  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
+
+  /// \brief Maximum number of micro-ops that may be scheduled per cycle.
+  unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
+
+  /// \brief Return the number of issue slots required for this MI.
+  unsigned getNumMicroOps(MachineInstr *MI) const;
+
   /// \brief Compute operand latency based on the available machine model.
   ///
   /// Computes and return the latency of the given data dependent def and use
@@ -82,11 +99,12 @@ public:
   /// occasionally useful to help estimate instruction cost.
   unsigned computeInstrLatency(const MachineInstr *MI) const;
 
-  /// \brief Identify the processor corresponding to the current subtarget.
-  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
+  /// \brief Output dependency latency of a pair of defs of the same register.
+  ///
+  /// This is typically one cycle.
+  unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
+                                const MachineInstr *DepMI) const;
 
-  /// \brief Maximum number of micro-ops that may be scheduled per cycle.
-  unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
 
 private:
   /// getDefLatency is a helper for computeOperandLatency. Return the