From 415af3452ea85f544761f8947426e4431706a165 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 15 Dec 2010 00:58:57 +0000 Subject: [PATCH] Add some missing patterns now that tLDRB and tLDRH are split into reg and immediate versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index c085a4e0526..965d3be927d 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1433,17 +1433,27 @@ def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; // If it's impossible to use [r,r] address mode for sextload, select to // ldr{b|h} + sxt{b|h} instead. +def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), + (tSXTB (tLDRBi t_addrmode_is1:$addr))>, + Requires<[IsThumb, IsThumb1Only, HasV6]>; def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, Requires<[IsThumb, IsThumb1Only, HasV6]>; +def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), + (tSXTH (tLDRHi t_addrmode_is2:$addr))>, + Requires<[IsThumb, IsThumb1Only, HasV6]>; def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, Requires<[IsThumb, IsThumb1Only, HasV6]>; def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; -def : T1Pat<(sextloadi16 t_addrmode_rrs1:$addr), - (tASRri (tLSLri (tLDRHr t_addrmode_rrs1:$addr), 16), 16)>; +def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), + (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; +def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), + (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; +def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), + (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; // Large immediate handling.