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Legalize BUILD_PAIR appropriately for upcoming 64 bit PowerPC work.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23776 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-10-18 00:27:41 +00:00
parent d41abfa1d2
commit 419f8b62f7
1 changed files with 25 additions and 0 deletions
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25
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -1605,6 +1605,31 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
break;
case ISD::BUILD_PAIR: {
MVT::ValueType PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
break;
case TargetLowering::Promote:
case TargetLowering::Custom:
assert(0 && "Cannot promote/custom this yet!");
case TargetLowering::Expand:
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
TLI.getShiftAmountTy()));
Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
break;
}
break;
}
case ISD::UREM:
case ISD::SREM:
case ISD::FREM: