6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-10 18:26:02 +00:00
Code Issues Projects Releases Wiki Activity

Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2011-10-12 01:05:13 +00:00
parent 6baabc1dd0
commit 41f9a430cb
2 changed files with 5 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/Mips/Mips64InstrInfo.td
View File

@@ -36,14 +36,6 @@ def imm32_63 : ImmLeaf<i64,
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
// Logical
let isCommutable = 1 in
class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>;
// Shifts
class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
SDNode OpNode, PatFrag PF>:
@@ -118,7 +110,7 @@ def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
def NOR64 : LogicNOR64<0x00, 0x27, "nor">;
def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
/// Shift Instructions
def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;

8
lib/Target/Mips/MipsInstrInfo.td
View File

@@ -292,10 +292,10 @@ class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
}
// Logical
class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"),
[(set CPURegs:$rd, (not (or CPURegs:$rs, CPURegs:$rt)))], IIAlu> {
[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
let shamt = 0;
let isCommutable = 1;
}
@@ -649,7 +649,7 @@ def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
def NOR : LogicNOR<0x00, 0x27, "nor">;
def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
/// Shift Instructions
def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;