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Remove the caching of the target machine from SystemZTargetLowering.

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Update all callers and uses accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-06-27 07:38:01 +00:00
parent d023a353c1
commit 4299a8b4ba
2 changed files with 33 additions and 21 deletions
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53
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -82,7 +82,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
: TargetLowering(tm, new TargetLoweringObjectFileELF()), : TargetLowering(tm, new TargetLoweringObjectFileELF()),
Subtarget(*tm.getSubtargetImpl()), TM(tm) { Subtarget(*tm.getSubtargetImpl()) {
MVT PtrVT = getPointerTy(); MVT PtrVT = getPointerTy();
// Set up the register classes. // Set up the register classes.
@ -673,11 +673,13 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
SystemZMachineFunctionInfo *FuncInfo = SystemZMachineFunctionInfo *FuncInfo =
MF.getInfo<SystemZMachineFunctionInfo>(); MF.getInfo<SystemZMachineFunctionInfo>();
auto *TFL = static_cast<const SystemZFrameLowering *>(TM.getFrameLowering()); auto *TFL = static_cast<const SystemZFrameLowering *>(
DAG.getTarget().getFrameLowering());
// Assign locations to all of the incoming arguments. // Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext()); CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
unsigned NumFixedGPRs = 0; unsigned NumFixedGPRs = 0;
@ -815,7 +817,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Analyze the operands of the call, assigning locations to each operand. // Analyze the operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext()); CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
*DAG.getContext());
ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
// We don't support GuaranteedTailCallOpt, only automatically-detected // We don't support GuaranteedTailCallOpt, only automatically-detected
@ -931,7 +934,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RetLocs; SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext()); CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
*DAG.getContext());
RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
// Copy all of the result registers out of their specified physreg. // Copy all of the result registers out of their specified physreg.
@ -962,7 +966,8 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
// Assign locations to each returned value. // Assign locations to each returned value.
SmallVector<CCValAssign, 16> RetLocs; SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext()); CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
*DAG.getContext());
RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
// Quick exit for void returns // Quick exit for void returns
@ -1786,8 +1791,8 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
const GlobalValue *GV = Node->getGlobal(); const GlobalValue *GV = Node->getGlobal();
int64_t Offset = Node->getOffset(); int64_t Offset = Node->getOffset();
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
Reloc::Model RM = TM.getRelocationModel(); Reloc::Model RM = DAG.getTarget().getRelocationModel();
CodeModel::Model CM = TM.getCodeModel(); CodeModel::Model CM = DAG.getTarget().getCodeModel();
SDValue Result; SDValue Result;
if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) { if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
@ -1824,7 +1829,7 @@ SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
SDLoc DL(Node); SDLoc DL(Node);
const GlobalValue *GV = Node->getGlobal(); const GlobalValue *GV = Node->getGlobal();
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
TLSModel::Model model = TM.getTLSModel(GV); TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
if (model != TLSModel::LocalExec) if (model != TLSModel::LocalExec)
llvm_unreachable("only local-exec TLS mode supported"); llvm_unreachable("only local-exec TLS mode supported");
@ -2287,9 +2292,9 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
// Use an addition if the operand is constant and either LAA(G) is // Use an addition if the operand is constant and either LAA(G) is
// available or the negative value is in the range of A(G)FHI. // available or the negative value is in the range of A(G)FHI.
int64_t Value = (-Op2->getAPIntValue()).getSExtValue(); int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
if (isInt<32>(Value) || TM.getSubtargetImpl()->hasInterlockedAccess1()) if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
NegSrc2 = DAG.getConstant(Value, MemVT); NegSrc2 = DAG.getConstant(Value, MemVT);
} else if (TM.getSubtargetImpl()->hasInterlockedAccess1()) } else if (Subtarget.hasInterlockedAccess1())
// Use LAA(G) if available. // Use LAA(G) if available.
NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT), NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
Src2); Src2);
@ -2602,7 +2607,8 @@ static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
MachineBasicBlock * MachineBasicBlock *
SystemZTargetLowering::emitSelect(MachineInstr *MI, SystemZTargetLowering::emitSelect(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
const SystemZInstrInfo *TII = TM.getInstrInfo(); const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
MBB->getParent()->getTarget().getInstrInfo());
unsigned DestReg = MI->getOperand(0).getReg(); unsigned DestReg = MI->getOperand(0).getReg();
unsigned TrueReg = MI->getOperand(1).getReg(); unsigned TrueReg = MI->getOperand(1).getReg();
@ -2650,7 +2656,8 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
unsigned StoreOpcode, unsigned STOCOpcode, unsigned StoreOpcode, unsigned STOCOpcode,
bool Invert) const { bool Invert) const {
const SystemZInstrInfo *TII = TM.getInstrInfo(); const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
MBB->getParent()->getTarget().getInstrInfo());
unsigned SrcReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(0).getReg();
MachineOperand Base = MI->getOperand(1); MachineOperand Base = MI->getOperand(1);
@ -2665,7 +2672,7 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
// Use STOCOpcode if possible. We could use different store patterns in // Use STOCOpcode if possible. We could use different store patterns in
// order to avoid matching the index register, but the performance trade-offs // order to avoid matching the index register, but the performance trade-offs
// might be more complicated in that case. // might be more complicated in that case.
if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) { if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
if (Invert) if (Invert)
CCMask ^= CCValid; CCMask ^= CCValid;
BuildMI(*MBB, MI, DL, TII->get(STOCOpcode)) BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
@ -2717,8 +2724,9 @@ SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
unsigned BinOpcode, unsigned BinOpcode,
unsigned BitSize, unsigned BitSize,
bool Invert) const { bool Invert) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32); bool IsSubWord = (BitSize < 32);
@ -2840,8 +2848,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
unsigned CompareOpcode, unsigned CompareOpcode,
unsigned KeepOldMask, unsigned KeepOldMask,
unsigned BitSize) const { unsigned BitSize) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32); bool IsSubWord = (BitSize < 32);
@ -2951,8 +2960,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
MachineBasicBlock * MachineBasicBlock *
SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI, SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
MachineBasicBlock *MBB) const { MachineBasicBlock *MBB) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
// Extract the operands. Base can be a register or a frame index. // Extract the operands. Base can be a register or a frame index.
@ -3067,8 +3077,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitExt128(MachineInstr *MI, SystemZTargetLowering::emitExt128(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
bool ClearEven, unsigned SubReg) const { bool ClearEven, unsigned SubReg) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
@ -3098,8 +3109,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI, SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
unsigned Opcode) const { unsigned Opcode) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
@ -3267,8 +3279,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
unsigned Opcode) const { unsigned Opcode) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent(); MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();

1
lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -249,7 +249,6 @@ public:
private: private:
const SystemZSubtarget &Subtarget; const SystemZSubtarget &Subtarget;
const SystemZTargetMachine &TM;
// Implement LowerOperation for individual opcodes. // Implement LowerOperation for individual opcodes.
SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;